COMP3221: Microprocessors and Embedded Systems Lecture 23: Memory Systems (II) Lecturer: Hui Wu Session 2, 2005

COMP3221/9221: Microprocessors and Embedded Systems 2 Overview Memory Timing Requirements

COMP3221/9221: Microprocessors and Embedded Systems 3 Memory Timing Requirements There are two components of timing requirements. Timing requirements from CPU.  CPU generates control signals such as READ/WRITE, and in the absence of handshaking signals such as WAIT or READY, takes data from or put data on the bus at specific times. Timing requirements from memory.  We will use SRAM as an example to illustrate the timing requirements from the point of view from the memory.

COMP3221/9221: Microprocessors and Embedded Systems 4 CPU Read and Write Cycles t CYC Cycle time: The total time to complete a write or read cycle. t AD Address delay: The delay from the start of the write or read cycle until the address appears on the external address bus. This delay accounts for multiplexing and other CPU-generated delay. t AV Address valid: The time the address is valid on the external address. The CPU takes it away or changes it at the end of the read or write cycle. The CPU control all reading and writing of information.

5 CPU Read Cycle t RED Read enable delay: The delay from the start of the read cycle until the read enable signal is asserted. This is found in CPUs that have separate READ and WRITE control signals. t RE Read enable pulse length: The duration of the READ signal. t RDD Read data delay: The CPU waits for this time before it reads the data from the data bus. t RDS Read data setup: The time the data must be valid before they are read by the CPU. t RDH Read data hold: The CPU may require the data to be held after it reads them.

6 CPU Read Cycle CPU Clock ADDRESS READ DATA Data Valid Address Valid t RDS t RDH t RDD t RE t RED t AV t AD t CYC

7 CPU Write Cycle t WDD Write data delay: The CPU waits for this time before it places the data to be written to memory on the data bus. t WDV Write data valid The time the CPU keeps the data on the data bus. t WED WRITE enable delay: The CPU waits for this time before it asserts the write enable signal. t WE Write enable pulse length: The during of WRITE signal. t WDH Write data hold: The time the CPU holds the data on the data bus after deasserting the write enable signal.

8 CPU Write Cycle CPU Clock ADDRESS WRITE DATA Data Valid Address Valid t WDV t WDD t RE t WE t AV t AD t CYC t WED t WDH

9 Memory Read Cycle t RC Read cycle: This the total time for the read cycle. t ACS Chip select access: The maximum time required by the memory for the CS to be asserted before the data are available. t AA Address access: This is the maximum time required by the memory for the address to be present before the data are available. t RDHA Read data hold after address: The time the memory may hold the data at the output after the address is changed. t RDHC Read data hold after chip select: The minimum time the chip will hold the data after being deselected.

10 Memory Read Cycle (Cont.) t OE Output enable access: On chips that have an output enable, this parameter gives the maximum time for the chip to respond with the data. t OHZ Output enable to out high Z: On chips that have an output enable, this parameter specifies the time the data will remain valid before going into three-state (high impedance). There are two times for reading data are important to memory designers. The read cycle time, t RC, is the minimum time that the address must be stable (unchanging) at the chip. The address access time, t AA, is the maximum time required by the memory before the data are available.

11 Memory Read Cycle (Cont.) ADDRESS CS OUTPUT ENABLE DATA Data Valid Address Valid t OHZ t OE t ACS t RDHA t RC t RDHC t AA

12 Memory Write Cycle t WC Write cycle: This is the minimum total time required by the memory to complete a write cycle. This may or may not the same as t RC. t CW Chip selection to end of write: The minimum time the CS signal must be asserted. t AS Address setup: The minimum time the address must be valid before the WRITE signal is asserted. t MWE Write enable: The minimum time the WRITE signal must be asserted. t AW Address valid to end of write: The minimum time the address must be valid.

13 Memory Write Cycle (Cont.) t WDS Write data setup: The minimum time the data must be valid before the end of write enable. t MWDHE Write data hold after enable: The minimum time the data must be valid before the WRITE signal is deasserted.

14 Memory Write Cycle (Cont.) ADDRESS CS DATA Data Valid Address Valid t WDS t WDHE t AS t WC t AW t CW t MWE WRITE

COMP3221/9221: Microprocessors and Embedded Systems 15 Reading 1.Chapter 9: Computer Memories. Microcontrollers and Microcomputers by Fredrick M. Cady