Edge-Triggered D Flip-Flops

Slides:

Advertisements

Similar presentations

//HDL Example 8-2 // //RTL description of design example (Fig.8-9) module Example_RTL (S,CLK,Clr,E,F,A);

Advertisements

Counters Discussion D8.3.

Verilog in transistor level using Microwind

CDA 3100 Recitation Week 11.

Shift Registers Module M11.1 Section 7.3.

Verilog Modules for Common Digital Functions

CPEN Digital System Design

COE 405 Design and Synthesis of DataPath Controllers Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals.

//HDL Example 5-1 // //Description of D latch (See Fig.5-6) module D_latch (Q,D,control); output Q; input.

Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.

//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.

How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.

Sequential Logic Latches and Flip-Flops. Sequential Logic Circuits The output of sequential logic circuits depends on the past history of the state of.

Digital Electronics Chapter 5 Synchronous Sequential Logic.

ReturnNext  Latch : a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal.

Latches and Flip-Flops Discussion D8.1 Section 13-9.

Arbitrary Waveform Discussion 5.5 Example 34.

Edge-Triggered D Flip-Flops Discussion D4.2 Example 26.

Registers VHDL Tutorial R. E. Haskell and D. M. Hanna T2: Sequential Logic Circuits.

Pulse-Width Modulated DAC

Conditional Statements  if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

Flip-Flops Module M10.2 Section 7.1. D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

A/D Converter Control Discussion D8.6 Rev. B – 3/14/2006.

A/D Converter Control Discussion D8.6. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.

Logic Design Review – 3 Basic Sequential Circuits Lecture L14.3 Verilog.

Ring Counter Discussion 11.3 Example 32.

Arbitrary Waveform Discussion 12.2 Example 34. Recall Divide-by-8 Counter Use q2, q1, q0 as inputs to a combinational circuit to produce an arbitrary.

Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

2-to-1 Multiplexer: if Statement Discussion D7.1 Example 4.

4-to-1 Multiplexer: Module Instantiation Discussion D7.2 Example 5.

//HDL Example 3-3 // //Stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay swd(A,B,C,x,y);

A/D Converter Datapaths Discussion D8.4. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

Design example Binary Multiplier.

Registers and Shift Registers Discussion D8.2. D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive.

Generic Multiplexers: Parameters Discussion D7.5 Example 8.

Multiplexers Lecture L6.6v Section 6.2. Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer.

Top-level Verilog Designs Discussion D9.1 Example 12.

D Flip-Flops in Verilog Discussion 10.3 Example 27.

Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

Digital Logic Review Discussion D8.7.

CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Introduction to Basys 2. Switches Slide switchesPush button switches.

Engineering 100 Section 250 Combinational Logic -- Examples 9/13/2010.

Figure 7.1. Control of an alarm system. Memory element Alarm Sensor Reset Set OnOff 

Latch Flip flop.

Introduction to Sequential Logic Design Flip-flops.

 Delay values control the time between the change in a right-hand-side operand and when the new value is assigned to the left- hand side.  Three ways.

Week Four Design & Simulation Example slides. Agenda Review the tiny example (Minako “logic”)from last week – look at the detailed static timing report.

Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.

Introduction to Sequential Logic Design Flip-flops.

ECE/CS 352 Digital System Fundamentals© 2001 C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapters 3 and 4: Verilog – Part 2 Charles R.

Chapter 5: Tasks, Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-1 Ders - 5 : Görevler,

Traffic Lights Discussion D8.3a. Recall Divide-by-8 Counter Use Q2, Q1, Q0 as inputs to a combinational circuit to produce an arbitrary waveform. s0 0.

1 COMP541 Sequential Circuits Montek Singh Feb 1, 2012.

Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Verilog Part 3 – Chapter.

M.Mohajjel. Continuous Assignments Continuously Drive a value onto a net Left hand side must be net Right hand side registers nets function calls Keyword.

Figure 7.6. Gated SR latch. (a) Circuit Q Q R S R S R Clk Q Q S Time (c) Timing diagram Clk ? ? SR xx Q(t) (no change) 0 1.

M.Mohajjel. Objectives Learn How to write synthesizable Verilog code Common mistakes and how to avoid them What is synthesized for what we code Digital.

Digital Electronics.

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 7 – Part 2.

Chapter 5: Tasks, Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-1 Chapter 5: Tasks, Functions,

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part4: Verilog – Part 2.

Supplement on Verilog FF circuit examples

Cascading 1-Bit Comparators

Pulse-Width Modulation (PWM)

Shift Registers Lecture L8.6 Section 8.3.

CS 140 Lecture 16 Professor CK Cheng 11/21/02.

Presentation transcript:

Edge-Triggered D Flip-Flops Discussion 10.2 Example 26

Edge-Triggered D Flip-Flop

// Example 26a: Edge-triggered D flip-flop module flipflop( input wire clk, input wire D, output q, output notq ); wire f1,f2,f3,f4,f5,f6; assign #5 f1 = ~(f4 & f2); assign #5 f2 = ~(f1 & f5); assign #5 f3 = ~(f6 & f4); assign #5 f4 = ~(f3 & clk); assign #5 f5 = ~(f4 & clk & f6); assign #5 f6 = ~(f5 & D); assign q = f1; assign notq = f2; endmodule

Aldec Active-HDL Simulation

Edge-Triggered D Flip-Flop with set and clear

// Example 26b: D flip-flop with clr and set module flipflopcs( input wire clk, input wire D, input wire set, input wire clr, output q, output notq ); wire f1,f2,f3,f4,f5,f6; assign #5 f1 = ~(f4 & f2 & ~set); assign #5 f2 = ~(f1 & f5 & ~clr); assign #5 f3 = ~(f6 & f4 & ~set); assign #5 f4 = ~(f3 & clk & ~clr); assign #5 f5 = ~(f4 & clk & f6 & ~set); assign #5 f6 = ~(f5 & D & ~clr); assign q = f1; assign notq = f2; endmodule

Aldec Active-HDL Simulation