Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont, CA 94538, USA Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA Michael L. Bushnell Rutgers University, Dept. of ECE, Piscataway, NJ 08854, USA

Jan. 29, 2002Gaur, et al.: DELTA'022 Talk Outline Problem Statement Background – Redundancy Identification Implication graph Partial implications Transitive closure Redundancy identification Results Conclusion

Jan. 29, 2002Gaur, et al.: DELTA'023 Problem Statement Many problems can be solved by implication graphs and transitive closure. We will study the problem of redundancy identification. Redundancy identification has applications in testing and in circuit optimization.

Jan. 29, 2002Gaur, et al.: DELTA'024 Redundancy Identification ATPG based method Exhaustive test pattern generation to find whether or not a target fault has a test. All redundant faults can be found, but ATPG cost is exponential in circuit size. Fault independent method Method analyzes circuit topology and function locally; no specific fault targeted. Many (not all) redundant faults can be found at a lower cost. FIRE, Iyer and Abramovici, VLSI Design’94. TC, Agrawal, Bushnell and Qing, ATS’96.

Jan. 29, 2002Gaur, et al.: DELTA'025 Use of Implication Graphs Implication graphs: Chakradhar, et al., Book’90 Larrabee, IEEE-TCAD’92 Transitive closure: ATPG: Chakradhar, et al., IEEE-TCAD’93 Redundancy, Agrawal, et al., ATS’96 Partial implications: Henftling, et al., EDAC’95 Gaur, MS Thesis’02, Rutgers University

Jan. 29, 2002Gaur, et al.: DELTA'026 Implication graph Nodes Two nodes per signal; nodes a and a correspond to signal a. A node has two states (true,false); represents the signal state. Edges A directed edge from node a to b means “a=1” implies “b=1”. An implication graph is a representation of logical implications between pairs of signals of a digital circuit.

Jan. 29, 2002Gaur, et al.: DELTA'027 Building an Implication Graph » If C is ‘1’ then that implies that A and B must be ‘1’, but the reverse is not true. Similarly, if either A or B is ‘0’ then C will be ‘0’. But if we want to represent the implications of A and B on C then partial implications are necessary. AC + BC + ABC = 0 ABAB C AB + C = 0 A BC A BC

Jan. 29, 2002Gaur, et al.: DELTA'028 Partial Implications AC + BC + ABC = 0 ABAB C AB + C = 0 A BC A BC Reference: Henftling, et al., EDAC, 1995

Jan. 29, 2002Gaur, et al.: DELTA'029 Observability Variables Observability variable of a signal represents whether or not that signal is observable at a PO. It can be true or false. ABAB C O C O A + BO A + O C BO A = 0 B O C B + O A = 0 OBOB OAOA O C = 1 (PO) OAOA OCOC

Jan. 29, 2002Gaur, et al.: DELTA'0210 Adding Observability Variables to Implication Graph A BC A BC O C O A + BO A + O C BO A = 0 B OAOA OCOC OCOC OAOA OCOC OAOA O B can be added similarly.

Jan. 29, 2002Gaur, et al.: DELTA'0211 Transitive Closure Transitive closure of a directed graph contains the same set of nodes as the original graph. If there is a directed path from node a to b, then the transitive closure contains an edge from a to b. ab c a b c d d A graph Transitive closure

Jan. 29, 2002Gaur, et al.: DELTA'0212 Stuck-at Fault Redundancy Detection of a fault requires the fault to be activated and its effect observed at a PO. Example: Fault a s-a-1 is detectable, iff following conditions can be simultaneously satisfied: a = 0 O a = 1

Jan. 29, 2002Gaur, et al.: DELTA'0213 Redundancy Identification by Transitive Closure a b c d e s-a-0 a bc d OcOc OdOd Implication graph (some nodes and edges not shown) Circuit with two redundant faults not found by FIRE or TC Implication Partial implication Transitive closure edge

Jan. 29, 2002Gaur, et al.: DELTA'0214 Method Summarized Obtain an implication graph from the circuit topology and compute transitive closure: Path-tracing algorithm (see this paper). Matrix method (see, Gaur, MS Thesis, Rutgers U., 2002). Examine all nodes: S-a-0 is redundant if the signal implies its complement. S-a-1 is redundant if the complement of the signal implies the signal. Both faults are redundant if the signal and its complement imply each other. S-a-0 is redundant if the signal implies its false observability variable. S-a-1 is redundant if the complement of the signal implies its false observability variable. S-a-0 is redundant if the observability variable implies the complement of the signal. S-a-1 is redundant if the observability variable implies the signal. Both faults are redundant if the observability variable and its complement imply each other.

Jan. 29, 2002Gaur, et al.: DELTA'0215 Classification of Redundant Faults by TC AND CircuitTotal red. +aborted faults* Tot. red. faults ident. Unexcit- able red. faults Unpropag- atable red. faults Undriv- able red. faults C C C C C C * HITEC, Nierman and Patel, EDAC’91

Jan. 29, 2002Gaur, et al.: DELTA'0216 FIRE and Transitive Clo. Circuit Name Tc no part (Sparc 5)FIRE* (Sparc 2)TC with part (Sparc 5) Red. flt. CPU s Red. flt. CPU s Red. flt. CPU s S S S S S S S S S *Iyer and Abramovici, VLSI Design’94

Jan. 29, 2002Gaur, et al.: DELTA'0217 Complexity of TC AND SUN Sparc 5

Jan. 29, 2002Gaur, et al.: DELTA'0218 Limitation of Method Observability variable of a fanout stem is not analyzed. Only the redundant faults due to false controllability of fanout stem can be identified. s-a-0 Three redundant s-a-0 faults identified by transitive closure s-a-1 Two redundant stem faults not identified by transitive closure

Jan. 29, 2002Gaur, et al.: DELTA'0219 Conclusion Partial implications improve redundancy identification. Present limitation of the method is the identification of redundancy due to the false observability of fanout stem; open problem. Transitive closure computation run times were linear in the number of nodes for the implication graphs of benchmark circuits, although the known worst-case complexity is O(N 3 ) for N nodes.