Data rate reduction in ALICE

Data volume and event rate TPC detector data volume = 300 Mbyte/event data rate = 200 Hz front-end electronics DAQ – event building Level-3 system permanent storage system bandwidth 60 Gbyte/sec 15 Gbyte/sec < 1.2 Gbyte/sec < 2 Gbyte/sec

Data rate reduction Volume reduction –regions-of-interest and partial readout –data compression entropy coder vector quantization TPC-data modeling Rate reduction –(sub)-event reconstruction and event rejection before event building

Regions-of-interest and partial readout (1) Selection of TPC sector and  -slice based on TRD track candidate Momentum filter for D 0 decay tracks based on TPC tracking

Regions-of-interest and partial readout (2) Momentum filter for D 0 decay tracks based on TPC tracking: p T > 0.8 GeV/c vs. all p T

Data compression: Entropy coder Variable Length Coding short codes for long codes for frequent values infrequent values Results: NA49: compressed event size = 72% ALICE: = 65% ( Arne Wiebalck, diploma thesis, Heidelberg) Probability distribution of 8-bit TPC data

Data compression: TPC - RCU TPC front-end electronics system architecture and readout controller unit. Pipelined Huffman Encoding Unit, implemented in a Xilinx Virtex 50 chip * * T. Jahnke, S. Schoessel and K. Sulimma, EDA group, Department of Computer Science, University of Frankfurt

Data compression: Vector quantization Sequence of ADC-values on a pad = vector: Vector quantization = transformation of vectors into codebook entries Quantization error: Results: NA49: compressed event size = 29 % ALICE: = 48%-64% (Arne Wiebalck, diploma thesis, Heidelberg) code book compare

Data compression: TPC-data modeling Fast local pattern recognition: Result: NA49: compressed event size = 7 % analytical cluster model quantization of deviations from track and cluster model local track parameters comparison to raw data simple local track model (e.g. helix)track parameters Track and cluster modeling:

Event rejection TRD Trigger ~2 kHz Global Trigger Zerosuppressed TPCdata Sectorparallel Other Trigger Detectors, L0pretrig. L1 L2accept (216 Links, 83 MB/evt) L0 Readout TPC Readout other detectors L1 Trackingof e + e - candidates insideTPC Select regionsof interest Verifye + e - hypothesis TRD e + e - tracks Reject event Tracksegments andspace points e + e - tracks plusROIs On-linedata reduction (tracking,reconstruction, partialreadout, compression) seeds enable L0 L1 L2 HLTHLT DAQ Time, causality MB/evt4-40 MB/evt Detector raw data readout for debugging Binary loss less data compression(RLE, Huffman, LZW, etc.) 45MB/evt Event sizes and number of links TPC only

Fast pattern recognition Essential part of HLT system –crude complete event reconstruction  monitoring, event rejection –redundant local tracklet finder for cluster evaluation and data modeling  efficient data compression –selection of ( , ,p T )-slices  ROI –momentum filter  ROI –high precision tracking for selected track candidates  event rejection

Requirements on the TPC-RORC design concerning HLT tasks Transparent mode –transfering raw data to DAQ Processing mode –Huffman decoding –unpacking –10-to-8 bit conversion –pattern recognition cluster finder Hough transformation tracker

TPC PCI-RORC HLT TPC PCI-RORC –backwards compatibility –fully programmable  FPGA coprocessor Simple PCI-RORC PCI bridgeGlue logic DIU interface DIU card PCI bus FPGA Coprocessor SRAM

raw data, 10bit dynamic range, zero suppressed Huffman encoding (and vector quantization) fast cluster finder: simple unfolding, flagging of overlapping clusters RCU RORC cluster list raw data fast vertex finder fast track finder initialization (e.g. Hough transform) Hough histograms Peakfinder receiver node Preprocessing per sector global node vertex position detector front-end electronics Huffman decoding, unpacking, 10-to-8 bit conversion

FPGA coprocessor: cluster finder Fast cluster finder –up to 32 padrows per RORC –up to 141 pads/row and up to 512 timebins/pad –internal RAM: 2x512x8bit –timing (in clock cycles, e.g. 5 nsec) 1 : #(cluster-timebins per pad) / 2 + #clusters  outer padrow: 150 nsec/pad, 21  sec/row 1. Timing estimates by K. Sulimma, EDA group, Department of Computer Science, University of Frankfurt – centroid calculation: pipelined array multiplier

FPGA coprocessor: Hough transformation Fast track finder: Hough transformations 2 –(row,pad,time)-to-(2/R, ,  ) transformation –(n-pixel)-to-(circle-parameter) transformation –feature extraction: local peak finding in parameter space 2. E.g. see Pattern Recognition Algorithms on FPGAs and CPUs for the ATLAS LVL2 Trigger, C. Hinkelbein et at., IEEE Trans. Nucl. Sci. 47 (2000) 362.

raw data, 8bit dynamic range, decoded and unpacked slicing of padrow-pad-time space into sheets of pseudo-rapidity, subdiving each sheet into overlapping patches track segments fast track finder B: 1. Hough transformation receiver node Processing per sector vertex position, cluster list sub-volumes in r, ,  cluster deconvolution and fitting updated vertex position updated cluster list, track segment list fast track finder B: 2. Hough maxima finder 3. tracklett verification RORC fast track finder A: track follower

Hough transform (1) Data flow

Hough transform (2)  -slices

Hough transform (3) Transformation and maxima search

FPGA coprocessor: Implementation of Hough transform

FPGA coprocessor prototype FPGA candidates –Altera Excalibur (256 kbyte SRAM) –Xilinx Virtex II (3.9 Mbit dual port SRAM Mbit distributed SRAM, 420 MHz) –external high-speed SRAM PCI bridgeGlue logic DIU interface DIU card PCI bus FPGA Coprocessor SRAM FEP RAM SIU interface SIU card RCU