FDR of the End-cap Muon Trigger Electronics 1/Mar./04 1 Beam Test of TGC electronics in 2003 Introduction Electronics Setup Stand-alone Run Setup Data Results Consistency of L1ID (event count), BCID (Bunch count) Validity of Trigger Beam Profile Delay curve (PP ASIC adjustment) Detection efficiency Trigger efficiency Combined Run Setup Results Chikara Fukunaga (TMU)

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 2 Introduction TGC electronics has been brought into H8 and made performance tests with actual muon beam in May and September 2003 when SPS has run in 25ns bunched mode. Two types of tests (Stand-alone test and combined one with RCP, MDT and MUCTPI) have been done.

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 3 Electronics Setup Chamber (Triplet 32(Strip) x 24(wire), Doublet both 32 chan.) ASD board (16ch.) x 2 PS pack PS board {8 PP (32 ch.) ASICs (Product.), 2 SLB ASICs (Proto. Version 2), 1 DCS } x2 Hi-pT crate Forward Type Hi-pT board (4 Hi-pT ASIC (Proto. Version 3 ~ final) x1 Proto. Star Switch (SSW) module x2 HSC ROD crates Sector Logic for r-  coincidence RODs (ROD and Test-ROD alternatively (May) or simultaneously (September)) TTCvi - TTCvx CCI Cables AWT twisted pair cable with 10 from ASDs to PS boards Individually shielded TP Category-5 cable from PS board to Hi-pT crate 10m (ATLAS:15m) for LVDS Optical fiber from Hi-pT crate to Sector Logic/ROD in the hut 30m (ATLAS:150m) for G-link.

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 4 Stand-alone Run Setup (1) TGC Setup itself is common for Combined run

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 5 T8 type chambers were used for all M1(Triplet), M2(Middle) and M3(Pivot). Trigger Electronics used were for forward type (PS-board, Hi-pT board) Channels M1 M2 M3 Wire Strip Stand-alone Run Setup (2) TGC Setup itself is common for Combined run T8 for M3 were used also for M2.

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 6 Readout data to be analysed in Stand-alone Run SLB output L1ID (Event count), BCID (Bunch count) Hit signal output (Hit map) Low-p T Trigger data for Wire and Strip SL output L1ID,BCID Trigger r-  coincidence information

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 7 Results (1) – Consistency of IDs Functionality of Bunch Counter Reset, Event Counter Reset Unique IDs synchronously detected in all the electronics components Check of readout data in Test-ROD ROD records errors in status word of Event Header during DAQ if discontinuities of event counter (L1ID) in TTCrq, discrepancy of L1ID in SLB with one given by TTCrq. discrepancy of Bunch count (BCID) in SLB with one by TTCrq, and time overflow of SSW input Check of ROD error detections in off-line analysis No error detected in Test-ROD. It is also confirmed with Off- line analysis with 3.3x10 5 events with two triggers (scintillater and TGC self)

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 8 Results (2) – Validity of Trigger Readout data are inputted to t1me simulation to get low-p T (SLB), high-p T (Hi-pT) and R-   SL  output expectation. Comparison of them in real-time with actually readout trigger data. No discrepancy found between data and simulation for 3.3x10 5 events

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 9 Summary of Data consistency Analysis Run No. Number of Events Trigger TypeRun Type ROD check Off-line check Trigger Validity r x10Stand-alone000 r x10Stand-alone000 r x10Stand-alone000 r x10Stand-alone x10Combined x10Combined x10Combined x10Combined x10Combined TGCCombined TGCCombined TGCCombined TGCCombined000

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 10 Results (3) Beam Profile M1 Triplet M2 Middle M3 Pivot 10cm  wire~5cm  strip~4.5cm

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 11 Delay Adjustment with PP ASIC AB A-B=5ns ~ 1.5m

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 12 Gate width Adjustment with PP ASIC TGCGate Width (ns) Delay (ns) M M M PP ASIC Setting Summary

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 13 Detection Efficiency Chamber efficiency (Wire)Chamber efficiency (Strip) M1 M2 M3 Lower Efficiency due to Wire support

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 14 Trigger Efficiency Overlap of wire supports in 2 Identical chambers for M2 and M3 Sector Logic Pt=6  p T  Efficiency of SL = 96.7% If M1 3 channel shift

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 15 Combined Run MDT,RPC,TGC and MuCTPI have made combined runs in September. Data Analysis from SFI file RPC ROD MDT ROD TGC ROD MuCTPI ROD ROS SFI

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 16 Summary of Combined run Data Analysis Run No.EventsTrigger Error 1 SL  MuCTPI Error 2 SL>MuCTPI Error 3 Bad BCID x x x x x TGC TGC TGC TGC0058 Error 1: Candidate found in SL is not equal to one in MuCTPI Error 2: Number of candidates in SL is more than in MuCTPI Error 3: BCID recorded in SL is not equal to one in MuCTPI

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 17 Correlation of SL and MuCTPI Correlation of SL and MuCTPI for p T and ROI have been clearly observed

FDR of the End-cap Muon Trigger Electronics 1/Mar./04 18 Summary of Beam Test Stand-alone test Consistency of BCID,L1ID in all the electronics components have been observed. Validity of trigger has been confirmed through comparison with simulation data Consistent Beam Profile has been observed. Delay and gate width adjustments have been worked. Bunch Crossing has been identified. Trigger efficiency could be maximised. Consistency of Low-pT and SL trigger data. Correct trigger data output with 40MHz bunched Muon beam Combined Run TGC trigger system could generate and distribute triggers for combined sub-detector system (RPC,MDT,TGC and MuCTPI). Although some TTC timing adjustment has not been achieved between MuCTPI and TGC, we found consistency of data between two systems.