© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 13 Direct Memory Access and DMA- Controlled I/O Barry B. Brey

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Direct Memory Access (DMA) is a method whereby the memory and I/O space of the microprocessor can be accessed directly without the intervention of the microprocessor or a program. During a DMA access the microprocessor is turned off by placing a logic one on the HOLD input. After placing a logic one on HOLD, the microprocessor issues a logic one on the HLDA to indicate a hold is in effect.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e During a HOLD, the microprocessor stops running the program and it places its address, data, and control bus connections at their impedance state. This in effect is the same as removing the microprocessor from its socket! While the microprocessor is held, other devices are free to gain access to its memory and I/O space to directly transfer data.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e HOLD has a higher priority than interrupts and HOLD takes effect in a clock or two. The only input with a higher priority than HOLD is the RESET input to the microprocessor.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Control Signals On early Intel microprocessor the control signals were not DMA compatible without additional circuitry. Because during a DMA, the memory and I/O are accessed simultaneously, 4 control signals are needed. The next slide illustrates a multiplexer used to generate these signals.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 8237 DMA Controller The chipset in a modern computer contains a pair of 8237 DMA controllers to provide 8 DMA channels. The only feature not supported by the chipset is the memory-to-memory DMA transfer described for the 8237 DMA controller integrated circuit. Intel removed this feature from the chipset because of the system architecture.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Command Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Mode Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Request Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Mask Set/Reset Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Mask Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Status Register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 8237 Port Assignments

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 8237 Channel Registers

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DMA Page Registers ChannelPort for A16–A23Port for A24–A31 087H487H 183H483H 281H481H 382H482H 48FH48FH 58BH48BH 689H489H 78AH486H

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that transfers a block of data using the 8237A ;DMA controller in Figure This is a memory-to-memory ;transfer. ;Calling parameters: ;SI = source address ;DI = destination address ;CX = count ;ES = segment of source and destination LATCHBEQU10H CLEARFEQU7CH CHOAEQU70H CH1AEQU72H CH1CEQU73H MODEEQU7BH CMMDEQU78H MASKSEQU7FH REQEQU79H STATUSEQU78H TRANSPROCNEAR USES AX MOV AX,ES;program latch B MOV AL,AH SHR AL,4 OUT LATCHB,AL OUT CLEARF,AL;clear F/L MOV AX,ES;program source address SHL AX,4 ADD AX,SI OUT CH0A,AL MOV AL,AH OUT CH0A MOV AX,ES;program destination address SHL AX,4 ADD AX,DI OUT CH1A,AL MOV AL,AH OUT CH1A,AL

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e MOV AX,CX;program count DEC AX OUT CH1C,AL MOV AL,AH OUT CH1C,AL MOV AL,88H;program mode OUT MODE,AL MOV AL,85H OUT MODE,AL MOV AL,1;enable block transfer OUT CMMD,AL MOV AL,0EH;unmask channel 0 OUT MASKS,AL MOV AL,4;start DMA OUT REQ,AL.REPEAT;wait for completion IN AL,STATUS.UNTIL AL & 1 RET TRANSENDP

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that clears the DOS mode video screen.= using the DMA ;controller as depicted in Figure ;Calling sequence: ;DI = offset address of area cleared ;ES = segment address of area cleared ;CX = number of bytes cleared LATCHBEQU10H CLEARFEQU7CH CHOAEQU70H CH1AEQU72H CH1CEQU73H MODEEQU7BH CMMDEQU78H MASKSEQU7FH REQEQU79H STATUSEQU78H ZERO EQU0 CLEARPROCNEAR USES AX MOV AX,ES;program latch B MOV AL,AH SHR AL,4 OUT LATCHB,AL OUT CLEARF,AL;clear F/L MOV AL,ZERO;save zero in first byte MOV ES:[DI],AL MOV AX,ES;program source address SHL AX,4 ADD AX,SI OUT CH0A,AL MOV AL,AH OUT CH0A

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e MOV AX,ES;program destination address SHL AX,4 ADD AX,DI OUT CH1A,AL MOV AL,AH OUT CH1A,AL MOV AX,CX;program count DEC AX OUT CH1C,AL MOV AL,AH OUT CH1C,AL MOV AL,88H;program mode OUT MODE,AL MOV AL,85H OUT MODE,AL MOV AL,03H;enable block hold transfer OUT CMMD,AL MOV AL,0EH;enable channel 0 OUT MASKS,AL MOV AL,4;start DMA OUT REQ,AL.REPEAT IN AL,STATUS.UNTIL AL & 1 RET CLEARENDP

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that prints data via the printer interface in ;Figure ;Calling sequence: ;BX = offset address of printer data ;DS = segment address of printer data ;CX = number of bytes to print LATCHBEQU10H CLEARFEQU7CH CH3AEQU76H CH1CEQU77H MODEEQU7BH CMMDEQU78H MASKSEQU7FH REQEQU79H PRINTPROCNEAR USES AX CX BX MOV EAX,0 MOV AX,DS;program latch B SHR EAX,4 PUSH AX SHR EAX,16 OUT LATCHB,AL POP AX;program address OUT CH3A,AL MOV AL,AH OUT CH3A,AL MOV AX,CX;program count DEC AX OUT CH3C,AL MOV AL,AH OUT CH3C,AL MOV AL,0BH;program mode OUT MODE,AL MOV AL,00H;enable block mode transfer OUT CMMD,AL MOV AL,7;enable channel 3 OUT MASKS,AL RET PRINTENDP

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e ;A procedure that tests for completion of the DMA action STATUS EQU 78H TESTP PROC NEAR USES AX.REPEAT IN AL,STATUS.UNTIL AL & 8 RET TESTP ENDP

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Input data streamRLL output

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e