Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 1 Low-Power Design and Test Dynamic and Static Power in CMOS Vishwani D. Agrawal Auburn University, USA Srivaths Ravi Texas Instruments India Hyderabad, July 30-31,

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 22 Components of Power  Dynamic  Signal transitions  Logic activity  Glitches  Short-circuit  Static  Leakage P total =P dyn + P stat P tran + P sc + P stat

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 23 Power of a Transition: P tran V DD Ground CLCL R on R = large v i (t) v o (t) i c (t)

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 24 Charging of a Capacitor V C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 25 i(t)=C dv(t)/dt=[V – v(t)] /R dv(t)V – v(t) ───=───── dt RC dv(t) dt ∫ ─────= ∫ ──── V – v(t) RC -t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V -t v(t)=V [1 – exp(───)] RC

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 26 -t v(t)=V [1 – exp( ── )] RC dv(t) V -t i(t)=C ───=── exp( ── ) dt R RC

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 27 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 -t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 28 Energy Dissipated per Transition in Resistance ∞ V 2 ∞ -2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 29 Energy Stored in Charged Capacitor ∞ ∞ -t V -t ∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt 0 0 RC R RC 1 = ─ CV 2 2

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 210 Transition Power  Gate output rising transition  Energy dissipated in pMOS transistor = CV 2 /2  Energy stored in capacitor = CV 2 /2  Gate output falling transition  Energy dissipated in nMOS transistor = CV 2 /2  Energy dissipated per transition = CV 2 /2  Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 211 Components of Power  Dynamic  Signal transitions  Logic activity  Glitches  Short-circuit  Static  Leakage P total =P dyn + P stat P tran + P sc + P stat

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 212 Short Circuit Power of a Transition: P sc V DD Ground CLCL v i (t) v o (t) i sc (t)

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 213 Short Circuit Current, i sc (t) Time (ns) 0 1 I sc Volt V DD i sc (t) 0 V i (t) V o (t) V DD - V Tp V Tn tBtB tEtE I scmaxf p-transistor starts conducting n-transistor cuts-off

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 214 Peak Short Circuit Current  Increases with the size (or gain, β) of transistors  Decreases with load capacitance, C L  Largest when C L = 0  Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 215 Short-Circuit Energy per Transition  E scf =∫ tB t E V DD i sc (t)dt = (t E – t B ) I scmaxf V DD / 2 = (t E – t B ) I scmaxf V DD / 2  E scf = t f (V DD - |V Tp | - V Tn ) I scmaxf / 2  E scr = t r (V DD - |V Tp | - V Tn ) I scmaxr / 2  E scf = E scr = 0, when V DD = |V Tp | + V Tn

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 216 Short-Circuit Energy  Increases with rise and fall times of input  Decreases for larger output load capacitance  Decreases and eventually becomes zero when V DD is scaled down but the threshold voltages are not scaled down

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 217 Short-Circuit Power Calculation  Assume equal rise and fall times  Model input-output capacitive coupling (Miller capacitance)  Use a spice model for transistors  T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 218 Short Circuit Power P sc =α f ck E sc

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 219 P sc, Rise Time and Capacitance V DD Ground CLCL R on R = large v i (t) v o (t) i c (t)+i sc (t) tftf trtr v o (t) ─── R↑ v o (t) V DD

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 220 i sc, Rise Time and Capacitance -t V DD [ 1- exp ( ───── )] v o (t) R↓(t) C I sc (t) =──── =────────────── R↑(t)

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 221 i scmax, Rise Time and Capacitance Small C Large C tftf 1 ──── R↑(t) i scmax v o (t) i t

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 222 P sc, Rise Times, Capacitance  For given input rise and fall times short circuit power decreases as output capacitance increases.  Short circuit power increases with increase of input rise and fall times.  Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 223 Summary: Short-Circuit Power  Short-circuit power is consumed by each transition (increases with input transition time).  Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power).  Increasing the output load capacitance reduces short-circuit power.  Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp |+V tn.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 224 Components of Power  Dynamic  Signal transitions  Logic activity  Glitches  Short-circuit  Static  Leakage

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 225 Leakage Power IGIG IDID I sub I PT I GIDL n+ Ground V DD R DrainSource Gate Bulk Si (p) nMOS Transistor

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 226 Leakage Current Components  Subthreshold conduction, I sub  Reverse bias pn junction conduction, I D  Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap  Drain source punchthrough, I PT due to short channel and high drain-source voltage  Gate tunneling, I G through thin oxide; may become significant with scaling

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 227 Subthreshold Current I sub = μ 0 C ox (W/L) V t 2 exp{(V GS –V TH ) / nV t } μ 0 : carrier surface mobility C ox : gate oxide capacitance per unit area L: channel length W: gate width V t = kT/q: thermal voltage n: a technology parameter

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 228 I DS for Short Channel Device I sub = μ 0 C ox (W/L)V t 2 exp{(V GS –V TH + ηV DS )/nV t } V DS = drain to source voltage η: a proportionality factor W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 229 Increased Subthreshold Leakage 0V TH ’V TH Log (Drain current) Gate voltage Scaled device IcIc I sub

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 230 Summary: Leakage Power  Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power.  For a gate it is a small fraction of the total power; it can be significant for very large circuits.  Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking.  Multiple-threshold devices are used to reduce leakage power.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 231 Technology Scaling  Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies  Constant electric field assumed

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 232 Constant Electric Field Scaling  B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp  Other forms of scaling are referred to as constant-voltage and quasi-constant- voltage.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 233 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 234 Technology Scaling  A scaling factor (S ) reduces device dimensions as 1/S.  Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm and 30nm.  A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston: Pearson Addison-Wesley, 2005, Section

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 235 Constant Electric Field Scaling Device Parameter Scaling Length, L 1/S Width, W 1/S Gate oxide thickness, t ox 1/S Supply voltage, V DD 1/S Threshold voltages, V tn, V tp 1/S Substrate doping, N A S

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 236 Constant Electric Field Scaling (Cont.) Device Characteristic Scaling β W / (L t ox ) S Current, I ds β (V DD – V t ) 2 β (V DD – V t ) 2 1/S Resistance, R V DD / I ds 1 Gate capacitance, C W L / t ox 1/S Gate delay, τ RC 1/S Clock frequency, f 1/ τ S Dynamic power per gate, P CV 2 f 1/S 2 Chip area, A 1/S 2 Power density P/A1 Current density I ds /A S

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 237 Problem: A Design Example  A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT.  Compare two power reduction strategies for extending the battery life: A.Clock frequency is reduced to half, keeping all other parameters constant. B.Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 238 Solution: Part A. Clock Frequency Reduction  Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task.  Energy consumption for the task will be, Energy = (P / 2 + P ) 2T = 3PT which is greater than the original 2PT.

Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 239 Solution: Part B. Supply Voltage Reduction  When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is, Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT  The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.