Top-level VHDL Designs

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Digital Logic with VHDL EE 230 Digital Systems Fall 2006 (10/17/2006)

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Presentation transcript:

Top-level VHDL Designs Discussion D3.2 Example 12

Top-level design of a quad 2-to-1 MUX and a hex to 7-segment decoder

-- Example 12: Top-level design library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux7seg is port( btn0 : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); a_to_g : out STD_LOGIC_VECTOR(6 downto 0); dp : out STD_LOGIC; an : out STD_LOGIC_VECTOR(3 downto 0) ); end mux7seg;

architecture mux7seg of mux7seg is component mux24a port( s : in std_logic; a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0)); end component; component hex7seg x : in std_logic_vector(3 downto 0); a_to_g : out std_logic_vector(6 downto 0)); signal y: STD_LOGIC_VECTOR(3 downto 0);

begin an <= "0000"; -- turn on all 4 digits dp <= '1'; -- decimal points off MUX1 : mux24a port map( s => btn0, a => sw(3 downto 0), b => sw(7 downto 4), y => y ); d74 : hex7seg x => y, a_to_g => a_to_g end mux7seg;

Aldec Active-HDL Simulation

.ucf file NET “an<0>" LOC = "E13" ; NET "an<1>" LOC = "F14" ; NET "an<2>" LOC = "G14" ; NET "an<3>" LOC = "d14" ; NET “a_to_g<6>" LOC = "E14" ; NET "a_to_g<5>" LOC = "G13" ; NET "a_to_g<4>" LOC = "N15" ; NET "a_to_g<3>" LOC = "P15" ; NET "a_to_g<2>" LOC = "R16" ; NET "a_to_g<1>" LOC = "F13" ; NET "a_to_g<0>" LOC = "N16" ; NET "dp" LOC = "P16" ;

Spartan 3 Board Note that all digits will display the same value