6/3/20151 Developing a multi-thread product – Introduction (ENCM491 – real time operating systems in 1 hr) M. Smith Electrical Engineering, University.

Slides:



Advertisements
Similar presentations
Computer Architecture
Advertisements

DSPs Vs General Purpose Microprocessors
Real-Time Library: RTX
1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.
A look at interrupts What are interrupts and why are they needed.
CSCI 4717/5717 Computer Architecture
1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 3: Input/output and co-processors dr.ir. A.C. Verschueren.
Lecture 9: D/A and A/D Converters
My attempt to multi-thread an audio talk-though program using batches of data M. Smith Electrical and Computer Engineering University of Calgary, Smithmr.
Boot Issues Processor comparison TigerSHARC multi-processor system Blackfin single-core.
Software and Hardware Circular Buffer Operations First presented in ENCM There are 3 earlier lectures that are useful for midterm review. M. R.
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 13 Direct Memory Access (DMA)
A look at interrupts What are interrupts and why are they needed in an embedded system? Equally as important – how are these ideas handled on the Blackfin.
Chapter 2: Processes Topics –Processes –Threads –Process Scheduling –Inter Process Communication (IPC) Reference: Operating Systems Design and Implementation.
3/5/2004DSP Applied to GPS Algorithms1 of 14 DSP Applied to GPS Algorithms.
A SINGLE FREQUENCY GPS SOFTWARE RECEIVER
Connectivity Lab University of California, Berkeley Location and Timing with C/A code in GPS Wanbin Tang Jan 24, 2007.
Chapter 4 Processor Technology and Architecture. Chapter goals Describe CPU instruction and execution cycles Explain how primitive CPU instructions are.
A look at interrupts What are interrupts and why are they needed.
TigerSHARC CLU Closer look at the XCORRS M. Smith, University of Calgary, Canada
Getting the O in I/O to work on a typical microcontroller Activating a FLASH memory “output line” Part 1 Main part of Laboratory 1 Also needed for “voice.
Just enough information to program a Blackfin Familiarization assignment for the Analog Devices’ VisualDSP++ Integrated Development Environment.
7/14/20151 Introduction toVisual DSP Kernel VDK for Multi-threaded environment ENCM491 – Real Time (in 1 hour) M. Smith, Electrical and Computer Engineering,
Pipelining By Toan Nguyen.
Numerical algorithms for power system protection Prof. dr. sc. Ante Marušić, doc. dr. sc. Juraj Havelka University of Zagreb Faculty of Electrical Engineering.
Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower.
Real time DSP Professors: Eng. Julian Bruno Eng. Mariano Llamedo Soria.
Ultra sound solution Impact of C++ DSP optimization techniques.
FINAL MPX DELIVERABLE Due when you schedule your interview and presentation.
CHAPTER 3 TOP LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION
The Functions of Operating Systems Interrupts. Learning Objectives Explain how interrupts are used to obtain processor time. Explain how processing of.
Interrupts, Buses Chapter 6.2.5, Introduction to Interrupts Interrupts are a mechanism by which other modules (e.g. I/O) may interrupt normal.
Computer Architecture Lecture 2 System Buses. Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given.
Ultra sound solution Profiles and other optimizations.
Support Across The Board ™ Visual DSP Kernel (VDK)
Fast Fault Finder A Machine Protection Component.
Over-view of Lab. 1 See the Lab. 1 web-site and the lecture notes for more details.
Multi-threaded projects Services and Drivers Alternate ways of doing Labs 1, 2, 3 and 4.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
Operating Systems 1 K. Salah Module 1.2: Fundamental Concepts Interrupts System Calls.
1 VxWorks 5.4 Group A3: Wafa’ Jaffal Kathryn Bean.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
1 SVY 207: Lecture 5 The Pseudorange Observable u Aim of this lecture: –To understand how a receiver extracts a pseudorange measurement from a GPS signal.
Introduction Contain two or more CPU share common memory and peripherals. Provide greater system throughput. Multiple processor executing simultaneous.
Over-view of Lab. 1 See the Lab. 1 web-site and latter lecture notes for more details.
© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Operating Systems Overview: Using Hardware.
Embedded Real-Time Systems Processing interrupts Lecturer Department University.
Topics Covered What is Real Time Operating System (RTOS)
Timer and Interrupts.
Embedded Systems Design
Developing a multi-thread Simulation of GPS system You’ll only need to add the threads – all functions (except correlation( )) provided M. Smith Electrical.
Chapter 6: CPU Scheduling
Software and Hardware Circular Buffer Operations
An Embedded Software Primer
Developing a multi-thread product -- Introduction
COP 4600 Operating Systems Spring 2011
Processor Fundamentals
ENCM K Interrupts Theory and Practice
Developing a multi-thread product -- Introduction
Convolution, GPS and the TigerSHARC XCORRS instr.
Single Value Processing Multi-Threaded Process
EE 472 – Embedded Systems Dr. Shwetak Patel.
VDK Concepts and Features How to Create a Project with VDK support
M. Smith Electrical and Computer Engineering University of Calgary,
Working with the Compute Block
Presentation transcript:

6/3/20151 Developing a multi-thread product – Introduction (ENCM491 – real time operating systems in 1 hr) M. Smith Electrical Engineering, University of Calgary ucalgary.ca

6/3/20152 / 45 References 1) Understanding GPS Principles and Applications, 1996, Elliott D. Kaplan 2) Digital Signal Processing – A Practical Approach, 1993, Emmanuel C. Ifeachor, Barrie W. Jervis 3) ADSP-TS101 TigerSHARC and Blackfin Processor Programming References, Analog Devices 4) Articles submitted to Circuit Cellar magazine by M. Smith, March 2004

6/3/20153 / 45 Introduction GPS traditionally done with ASIC/Processor combination Looking at FPGA/DSP combination for low end GPS receivers Technological interest in software radio  Cheaper, quicker development cycle.  Customizations for special applications From a talk by Darrell Anklovitch for ENEL619.23

6/3/20154 / 45 What is GPS? Global Positioning System 24 satellite (SV) constellation Orbits are set-up to give global coverage 24 hours a day Need at least 4 satellites in view to calculate a position Orbiting 20,000 km from the surface of the Earth in 12 hour cycles (1)

6/3/20155 / 45 GPS Positioning Concepts (1) For now make 2 assumptions:  We know the distance to each satellite  We know where each satellite is Require 3 satellites for a 3-D position in this “ideal” scenario Requires 4 satellites to account for local receiver clock drift.

6/3/20156 / 45 GPS Signal Structure Each satellite transmits 2 carrier frequencies referred to as L1 (1575 MHz) and L2 (1227 MHz) Each carrier frequency is BPSK modulated with a unique PRN (pseudo random number) code The PRN code on L1 is called CA code (coarse acquisition), The PRN code on L2 is called P code (precise) CA code takes 1 ms for full PRN transmission at 1MHz chip (bit) rate. P code takes 1.5 s for full PRN transmission at ~10MHz chip rate Also modulated on each carrier is 50 Hz data that includes the current position of the satellite

6/3/20157 / 45 Determining Time Use the PRN code to determine time Use time to determine distance to the satellite distance = speed of light * time (1)

6/3/20158 / 45 Algorithms to Find PRN Phase Time-domain Cross correlation: 1/N ∑ x 1 (n) * x 2 (n)  Coding equivalent to FIR filter, but need to filter N sets of data, each shifted by one data point – looks like a final exam question to me. Correlation of perfectly matching signals gives a maximum value Correlation of 2 random data sequences tends to 0  PRN code from different satellites are designed to correlate to 0. Frequency domain correlation: 1/N F -1 [X 1 (k)X 2 (k)] where F -1 is the inverse Discrete Fourier Transform and the X’s are the Discrete Fourier Transforms of two sequences D

6/3/20159 / 45 Frequency Domain 1/N F -1 [X 1 (k)X 2 (k)]  1024 point FFT(2 * NLOG 2 N)  1024 MULTS(N)  1024 point INV FFT(NLOG 2 N) Time Domain 1/N ∑ x 1 (n) * x 2 (n) n = 0  1024 MACs(N)  1024 Phases(N) Timing 30,000 Complex operations 1,048,576 operations N-1 (N 2 )

6/3/ / 45 TigerSHARC -- TS101 and TS201 Low-cost version $45 / chip Evaluation boards $950 each educational price TS101 TS201 Can do “COMPLEX” arithmetic

6/3/ / 45 Implementing a multi-thread system working on batch data – “audio example” Collect N 44 kHz  array1 Collect N 44 kHz  array2 Collect N 44 kHz  array3 Collect N 44 kHz  array1 Collect N 44 kHz  array2 Process array1 Process array2 Process array3 Process array4 Transmit N 44 kHz  array1 Transmit N 44 kHz  array2 Transmit N 44 kHz  array3

6/3/ / 45 Implementing a multi-thread system -- “audio example” Collect N 44 kHz  array1 Collect N 44 kHz  array2 Collect N 44 kHz  array3 Collect N 44 kHz  array1 Collect N 44 kHz  array2 Move array1  array4 SimulateComplex Move array2  array5 SimulateComplex Move array3  array6 SimulateComplex Move array1  array4 SimulateComplex Transmit N 44 kHz  array4 Transmit N 44 kHz  array5 Transmit N 44 kHz  array6

6/3/ / 45 Essentially Take an audio Talk-through program for loop { Read_a_sample; Perform operation; Write_a_sample; } Turn into 5-threads running under interrupts  Idle thread  Initialization thread – sets up system, when ready – launches the other threads – then activates the first thread  ReadValueThread,  ProcessValueThread – with simulated Complex Algorithm  WriteValueThread

6/3/ / 45 Initialization Thread

6/3/ / 45 Main Thread – example

6/3/ / 45 Need to investigate and understand system behaviour and limitations Concept of task priority

6/3/ / 45 Using real-time audio-threads -- Write

6/3/ / 45 VDK – Status History

6/3/ / 45 Adding the Initialization thread

6/3/ / 45 Making the InitializationThread a “Boot Thread”

6/3/ / 45 Add the thread programming control

6/3/ / 45 Avoid the free-running code

6/3/ / 45 Then add semaphores to control flow

6/3/ / 45 Essential, if not exact, concept of multi- threading code Do all the initial preparation of the board  Set up stack  Set up “C/C++” environment  Set up processor timer Default on Blackfin ADSP-BF533 board – every 0.05 ms (called a TIC) an interrupt occurrs Start with an IDLE Thread When first TIC occurs – the interrupt handler will cause the Scheduler ISR to run

6/3/ / 45 Scheduler ISR Save all the registers (etc) of the IDLE thread to the IDLE thread context buffer Recover all the registers for the scheduler ISR context buffer (saved somewhere during the initialization procedure) There had better be a boot thread – otherwise system hangs  VDK tool will not let you build a system without at least one boot thread Decide which boot thread has the highest priority? Save all the registers from the Scheduler ISR back into the context buffer Recover all the registers for the boot thread from its context buffer Return from ISR  We have now performed a “context switch” between the IDLE thread and the BOOT thread.

6/3/ / 45 Boot thread The boot thread now executes until the first TIC occurs (next ISR call) We now switch back into Scheduler  Save all the registers (etc) of the FIRST BOOT THREAD thread to the thread context buffer  Recover all the registers for the scheduler ISR context buffer Other threads need launching?  If there are other Boot threads then launch them depending on their priority and the ROUND ROBIN scheduling behaviour set by the programmer for tasks of equal priority  If a boot thread has requested that other threads need launching then launch those. Unclear when the VDK::CreateThread operation occurs

6/3/ / 45 The launching of threads Looks like threads get launched “during a TIC” – meaning that another context switch occurs for each VDK::CreateThread ( ) Does that apply to VDK::PostSemaphores( ) too?

6/3/ / 45 Back in scheduler Other threads need launching?  If there are other Boot threads then launch them depending on their priority and the ROUND ROBIN scheduling behaviour set by the programmer for tasks of equal priority  If a boot thread has requested that other threads need launching then launch those. Have threads posted semaphores?  Store them in a “posted semaphore table.  Threads can also post “messages” but I have not worked that out yet Are threads pending semaphores?  Depending on which task is running now, and its relative priority to tasks that are pending semaphores then either perform context switching or not  How do you handle conflicts? I think that is my problem with my final version of Lab. 5 part 3

6/3/ / 45 Original audio-talk through program ISR routine Channel to Channel Copy Multi-tasking version of ISR routine

6/3/ / 45 Step 1 – Add Talk-through program

6/3/ / 45 Step 2 – Investigate Thread Behaviour

6/3/ / 45 Step 3 – Fix Thread Behaviour

6/3/ / 45 Step 4 – Start migrating code to the various threads -- Fix ISR behaviour ORIGINAL NEW VERSION

6/3/ / 45 Fix Thread Behaviour Initialization thread  Creates other threads and then waits for ever ReadThread  Moves my_In Value  Process Value ProcessThread  Moves Process Value  ProcessDone Value  Calls a “non-optimizable to nothing” routine SimulateMoreComplexProcess(cycles_to_waste) WriteThread  Moves ProcessDone Value  my_Out Value

6/3/ / 45 Final ReadThread

6/3/ / 45 Final ProcessThread

6/3/ / 45 Final WriteThread

6/3/ / 45 Thread Behaviour depends on Task priorities ALL TASKS HAVE EQUAL PRIORITY WRITE TASK HAS HIGHER PRIORITY THAN PROCESS TASK 1) Read Task – sends semaphore to Process Task 2) Process Task – sends semaphore to Write Task and “starts to waste cycles” 3) Scheduler determines that Write Task can start, send semaphore to Read Task, and finish – and then 4) Scheduler lets Process Task finish (? Why not let Read Task restart?)

6/3/ / 45 Thread Behaviour Useless as system is “free running” and the signals input and output have no relationship to samples generated by ISR  Some samples repeated many times, others are not  Number of repeats depends on the time that ProcessThread takes to execute

6/3/ / 45 Need to add an ISR semaphore

6/3/ / 45 Read Thread – starts on ISR semaphore Blackfin Assembly code looks like 68K With LINK, UNLINK, RTS instructions MACRO STANDARD APPROACH VDK::PostSemaphore( ) DOES NOT WORK

6/3/ / 45 Many issues still need handling How much time is available before losing sound quality? What are the best priorities for the tasks, and does that priority depend on how much time is spent in ProcessTask? What is the best setting for the task scheduler TIC time (based on processor internal timer)?  Too fast – too much time saving / recovering registers during task switching  Too slow – problems with interrupts being missed or values being over-writtem

6/3/ / 45 Scheduling based on TIC time DEFAULT TIC = 0.05 ms TIC = ms Don’t forget – TICs are shortened

6/3/ / 45 Which is the Slower / Faster TIC time? Question – how does the thread status history reflect sound quality?