6/3/2015 SHARC99 Conference Copyright M. Smith This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab Type in action items as they come up Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered. SHARC99 Conference, U.K. November/December, 1999 Finite Precision Effects in Digital Filter Implementations L. E. Turner and M. R. Smith, University of Calgary, Alberta, Canada

6/3/2015 SHARC99 Conference Copyright M. Smith Format for the Day Why worry? Finite Precision Effects –Multiplier Coefficient Quantization –Signal Quantization –Filter Structure Effects DIGICAP -- Tool details not covered in paper –Filter Response Calculation –Quantization Effect Calculation –Availability Conclusion

6/3/2015 SHARC99 Conference Copyright M. Smith Why bother? If the filter implementation is incorrect then Incorrect final design Special advantages in newer processor architecture are wasted Problem can be overcome in many cases

6/3/2015 SHARC99 Conference Copyright M. Smith Example -- IIR filter Direct Form third-order digital Infinite duration Impulse Response Chebychev filter

6/3/2015 SHARC99 Conference Copyright M. Smith Theoretical Filter Response Filter Coefficients b1 = PASS BAND b2 = b3 = ZOOMED PASS BAND

6/3/2015 SHARC99 Conference Copyright M. Smith Problems -- Finite number of bits Register Width Data Bus width -- Memory Multiplication truncation Accumulation truncation Many designers familiar with need to scale input to avoid overflow problems when using integer processors

6/3/2015 SHARC99 Conference Copyright M. Smith Trying to avoid non-ideal effects of finite number of bits during mathematical operations d3d2d1d0????ss? d6d5d4 16-bit integer format Overflow protection Underflow protection Where is the best location to place an 8-bit input signal within a 16-bit integer format? Algorithm dependent

6/3/2015 SHARC99 Conference Copyright M. Smith Floating point processors are not immune from the effect of truncation d6d5d4d3d2d1d0?s??? SHARC 16-bit short word floating point format 1. f10 ……….. f0 s e3 …….. e0 16-bit float -- Seems to be only 11-bits really available before non-ideal effects come into account -- but see later Floating point operations -- only scale as, and when needed -- convenient -- actually less accurate than equivalent word length integer

6/3/2015 SHARC99 Conference Copyright M. Smith Truncation effects have effect on Filter response directly “Ideal” b2 = “Actual” b bit precision –6 bits and a sign –value = ( 52 / 64) –Truncated because of architecture –OR, effectively truncated because of overflow or underflow protection concerns

6/3/2015 SHARC99 Conference Copyright M. Smith Direct Form Filter Coefficient Quantization Filter responses using quantized filter coefficients are calculated using the tool DIGICAP available from the L. E. Turner at University of Calgary 7-bits QUANTIZED COEFFICIENTS IDEAL

6/3/2015 SHARC99 Conference Copyright M. Smith Solutions Modify each filter coefficient in a different manner to minimize the error. –Random Hacking (Guessing) –Simulated Annealing -- see references -- coefficient polishing Change filter form so that filter characteristics are generally less sensitive to truncation effects –LDI filters for example based on Ladder Filter Topology

6/3/2015 SHARC99 Conference Copyright M. Smith 3rd order Chebychev filters IDEAL QUANTIZED 7-bits DIRECT LDI IDEAL QUANTIZED 7 bits

6/3/2015 SHARC99 Conference Copyright M. Smith Signal Quantization Overflow can occur when the manipulation (addition, subtraction or multiplication) of a value at a node results in a number that can’t be represented in the finite-number representation used –determined by effective word length available) Overflow counter-balanced by –Sufficient available bits in data path –Scaling of input and internal values -- division, BUT scaling results in loss of precision, non-linearity, limit cycles, dead bands

6/3/2015 SHARC99 Conference Copyright M. Smith Determining effect of signal quantization Real life division can be represented by an “ideal division operation” + error source

6/3/2015 SHARC99 Conference Copyright M. Smith Ameliate overflow and underflow by use of guard bits d3d2d1d0????????d7d6d5d4 16-bit integer format Overflow protection Underflow protection Top guard bits -- overflow protection Bottom guard bits -- quantization error protection

6/3/2015 SHARC99 Conference Copyright M. Smith Overflow Protection Determine maximum gain between Input and any internal node using Bounded Input/Bounded Output response using L1Norm values L1(IN, OUT1) L1(IN, OUT2) L1(IN, DELAY1) L1(IN, DELAY2) L1(IN, DELAY3) Maximum gain Allow for gain of 4 Requires 2 additional sign (guard) bits L1Norms determined with DIGICAP tool

6/3/2015 SHARC99 Conference Copyright M. Smith Quantization Protection Determine gain between any internal node and the output using L1Norm values and then SUM possible error gains L1(OUT1, OUT2) L1(DELAY1, OUT2) L1(DELAY2, OUT2) L1(DELAY3, OUT2) Error gain possible Allow for ERROR gain of 8 Requires 3 additional quantization (guard) bits L1Norms determined with DIGICAP tool

6/3/2015 SHARC99 Conference Copyright M. Smith Final filter design required (software or hardware) ANTI-OVERFLOW ANTI-QUANTIZATION ERROR

6/3/2015 SHARC99 Conference Copyright M. Smith 8 and 12 bit input signal bit integer d1d0QE ???sssd6d5d4d3d2 Overflow protection Quantization protection d1d0sd6d5d4d3d2 8-bits of useable signal d5d4d3d2d1QE sssd10d9d8d7d6 For a 12-bit input signal 1 bit of output lost to precision effects Usable signal

6/3/2015 SHARC99 Conference Copyright M. Smith 8-bit input Floating point processor as integer processor d5d4d3d2d1QE sssd6 SHARC 16-bit short word floating point format d1QEsd6d5d4d3d2 Useable signal? Loss of 1 bit Strictly valid? Remember 1.frac format and exponent bits Exponent Useful bits or not?

6/3/2015 SHARC99 Conference Copyright M. Smith 12-bit input signal on FP processor d9d8d7d6d5QE sssd10 SHARC 16-bit short word floating point format Exponent Useful bits or not? 5 bits lost? Remember 1.frac format and exponent bits Significant loss of bits if this picture is correct interpretation Considering the actual architecture of floating point processor becomes important

6/3/2015 SHARC99 Conference Copyright M. Smith Re-interpretation of FP guard bits d3d2d1NE QE sd6d5d4 8-bit input on 16-bit FP format NE Bits -- inaccurate because of quantization noise during FP normalization operations to avoid overflow QE Bits -- lost because of truncation not associated with normalization d7d6d5NE QE sd10d9d8 12-bit input on 16-bit FP format

6/3/2015 SHARC99 Conference Copyright M. Smith Re-interpretation valid? Not entirely -- Consider 16-bit FP representation 1-bit sign 4 bit exponent 11 bits representing 13 bits of signal because of 1.frac representations + sign bit d2d1d0NE QE sd5d4d3 8-bit input with 16-bit FP format D6 is at worse the 1 in 1.frac No bits lost if 8-bit input

6/3/2015 SHARC99 Conference Copyright M. Smith Worse case quantization effect on SHARC processor –Packed 16-bit floating point analyse as if for 13-bit integer processor –Standard 32-bit single precision FP analyse as if for 25-bit integer processor –40-bit Extended Precision FP analyse as if for 33-bit integer processor

6/3/2015 SHARC99 Conference Copyright M. Smith DIGICAP An Analysis Tool Contact

6/3/2015 SHARC99 Conference Copyright M. Smith DIGICAP Tool -- 1 Analyse and implements one dimensional digital filters constructed using multipliers, delay elements, inputs, outputs and summing nodes Filter circuit entered as direct signal flow graph Algorithm represented as a signal flow graph Capable of calculating time or steady state sinusoidal frequency domain responses with full or finite precision.

6/3/2015 SHARC99 Conference Copyright M. Smith DIGICAP Tool -- 2 Capable of computing and displaying z-domain transfer functions (no multiple poles) State matrix representation of difference equation L1Norm Schedule of filter operations Descriptive program listings suitable for different filter implementations –“C” code –TI320 assembly code –FIRST silicon compiler (bit-serial) –SHARC (not yet)

6/3/2015 SHARC99 Conference Copyright M. Smith input n1 ac delay n2 n3 delay n3 n4 delay n4 n5 mult n3 n2 -b1 mult n4 n2 -b2 mult n5 n2 -b3 mult n1 n2 1 mult n2 n6 1 output n6 DIGICAP Description N1N2 N5 N6 N3N4

6/3/2015 SHARC99 Conference Copyright M. Smith Typical DIGICAP Control parameters n_precision n.m (node precision) –n = total bits, m bits to right of binary point (m = 0 for integer arithmetic) n_quanttype (coefficient precision) –magnitude, round, floating etc checkcoeff (design warning) –Coefficient can’t be represented in n.m add_time, multiply_time (parallelism) 100 page manual available

6/3/2015 SHARC99 Conference Copyright M. Smith DIGICAP Availability Have a DOS version of the disk with me –contact me later with a blank disk Contact -- Dr. L. E. Turner enel.ucalgary.ca for DIGICAP user manual and diskette Also available on the web from

6/3/2015 SHARC99 Conference Copyright M. Smith Thanks and References Financial support from University of Calgary and NSERC (Natural Sciences and Engineering Research Council of Canada) Other DIGICAP Developers –D.A. Graham, S. D. Worthington, D.R. Motyka and B. D. Green DIGICAP Users Guide -- L. E. Turner, 1989, 1992 R. Kacelenga et al., IEEE Int. Symp. Circuits and Systems, New Orleans 1990 Turner et al., IEEE Trans. Education, May 1993