Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

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Presentation transcript:

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Testing of VLSI Circuits and Power High circuit activity during test leads to functional slowdown and high test power dissipation: –Peak power - Large IR drop in power distribution lines Voltage droop and ground bounce (power supply noise) Reduced voltage slows the gates down (delay fault) –Average power - Excessive heating Timing failures Permanent damage to circuit –Good chip may be labeled as bad → yield loss Existing solution: Use worst-case test clock rate to keep average and peak power within specification. –Results in long test time. 3/14/2011ICIT-SSST'112

Problem Statement Reduce test time without exceeding the power specification: Proposed solution: Adaptive test clock Use worst-case clock rate when circuit activity is not known Monitor circuit activity and speed up the clock when activity reduces 3/14/2011ICIT-SSST'113

Built-In Self-Test (BIST) 3/14/2011ICIT-SSST' Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

RBG Generates /14/2011ICIT-SSST' Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

RBG Generates /14/2011ICIT-SSST' Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

Main Idea 3/14/2011ICIT-SSST'11 7 Observation: Different sequences of test vector bits consume different amounts of power. Conventional test clock frequency is chosen based on maximum test power consumption. All test vector bits are applied at the same frequency. Test vector bit sequences consuming lower power can be applied at higher clock frequencies without exceeding power budget of the chip.

Speeding Up Scan Clock 3/14/2011ICIT-SSST'11 8 Clock periods Cycle power Power budget Clock periods Cycle power Power budget

Monitoring Test Activity 3/14/2011ICIT-SSST' Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator Non-transition monitor SSR, RBG and RA have common clock and reset Test multiplexers

A Dynamic Scan Architecture 3/14/2011ICIT-SSST'1110

Clock Rate vs. SSR Activity 3/14/2011ICIT-SSST'1111 fmax fmax/2 fmax/3 fmax/4 0 N/4 2N/4 3N/4 N Number of non-transitions counted Clock rate N N/2 N/4 0 SSR transitions per clock N = number of flip-flops in scan shift register (SSR) M = number of adjustable clock rates = 4, in this illustration

Dynamic Control of Scan Clock 3/14/2011ICIT-SSST'1112 Monitor number of transitions in scan chain Speed-up scan clock when activity in scan chain is low or slowdown scan clock when activity in scan chain is high Number of flip-flops in scan shift register (SSR), N = 8 Number of adjustable clock rates, M = 4 Maximum clock rate, fmax = f

3/14/2011ICIT-SSST'1113 Circuit Number of Scan flip- flops Number of clock rate steps Test time reduction (%) Area overhead (%) ExperimentTheory s s s s s s s ISCAS89 Benchmark Circuits

S386: Activity for One Scan-In 3/14/2011ICIT-SSST'1114 Input activity = 25% Time reduction = 22.5%

3/14/2011ICIT-SSST'1115 Circuit Number of scan flip-flops Number of clock rate steps Test time reduction (%) u d d f q p a ITC02 Benchmark Circuits

Improvement: Monitor Input & Output 3/14/2011ICIT-SSST'1116

Conclusion Dynamic control of scan clock rate reduces test time without exceeding power specification. Vectors with low average scan-in activity and high peak activity give more reduction in test time. Up to 50% reduction in test time is possible. References: P. Shanmugasundaram, Test Time Optimization in Scan Circuits, Master’s Thesis, Department of ECE, Auburn University, Auburn, Alabama, December P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit,” Proc. 29 th IEEE VLSI Test Symposium, May 2-4, /14/2011ICIT-SSST'1117