Jack Ou, Ph.D. CES522 Engineering Science Sonoma State University

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Presentation transcript:

Jack Ou, Ph.D. CES522 Engineering Science Sonoma State University Verilog Tutorial 3 Jack Ou, Ph.D. CES522 Engineering Science Sonoma State University

Outline Motivation Blocking Assignments Non-Blocking Assignments

Shift Register Using Blocking Assignments

Test Bench for the Shift Register Clock cycle: 10 intervals Input (E) changes state Every 40 intervals

Output E is updated every 40 cycles A is updated 30 intervals after E

A=Delayed E

Reverse Update Algorithm

= The assignment operator (=) causes statements to be executed in the listed order, with the storing of value occurring immediately after any statement can executed and before the next statement. Order matter!!! = is used with blocked statements.

<= Nonblocking assignments are made with the nonblocking assignment operator (<=)instead of the assignment operator. Nonblocking assignment statements effectively execute concurrently ( in parallel) rather than sequentially, so the order in which they are listed has no effect.

Shift Register using <=