EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB P A R A L L E L C O M P U T I N G L A B O R A T O R Y EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB RAMP Wrap Wrap Krste Asanovic RAMP Wrap Stanford, CA August 25, 2010

EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB Not the end of FPGA Arch Simulation Research  Many projects running at full throttle improving FPGA simulation ideas  Lots of work to do on modeling various microarch components (vector units, DMA, interconnect, caches, I/O devices, …) But….  Area mature enough to publish in major conference venues (ISCA, ISPASS)  Usable for “production” research 2

EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB Great Collaboration Success  Although ~no IP shared (save the DRAM memory controller), a very open collaboration in terms of idea exchange  Hard to truly tease apart where each idea originated/matured among the group  This idea collaboration was much more valuable than any lump of IP (save the DRAM memory controller)  Thanks to all the students and PIs across all the institutions and our sponsors. 3

EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB What’s Next for the Group?  Making hardware design more productive  Put CS back into hardware development  Languages/tools for RTL design  Design-space exploration key to design efficiency  Not good enough to get one design working, want to find best design  Have to write generators not build point designs  App-specific chip generators  Parameterizable manycore as basis of future SoC designs  Participants:  Arvind, Asanovic, Chiou, Emer, Hoe, Horowitz, Wawrzynek 4

EECS Electrical Engineering and Computer Sciences B ERKELEY P AR L AB What’s Next Today?  6-7PM Poster/Demo Session  7PM Dinner  Both in the Packard Atrium 5