1 Delay Insensitivity does not mean slope insensitivity! Vainbaum Yuri

2  Delay Insensitivity does not mean slope insensitivity! Paper presented in NOC-2010  Authors : Florent Ouchet, Katell Morin-Allory, Laurent Fesquet - TIMA Laboratory

3 Talk outline Phenomenon highlight C-element implementation models C-element robustness for slow slopes Improving C-element impelemetaton Area/power penalty analysis

4 Asynchronous circuit quality Self-timed circuit robustness evaluation: PVT variations Chip aging: transistors, nets, vias… Low supply voltage Harden the behavior in harsh environment Avoid dead locks Avoid wrong operations

5 Asynchronous circuit quality-Slopes Local effects on the circuit:  Very slow signal variations  Slow slopes on pads and nets Ex.: In synchronous design slopes are treated carefully  Tools developed to check slopes  Designer must fix all slope’s violations

6 Asynchronous circuit quality-Slopes  Self-timed circuit assumptions usually reduced to delays  But slopes must be considered

7 2 half-buffers

8 1 fast output environment

9 2 half-buffers 1 fast output environment 1 slow input environment

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17 Slow slop!

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19 Slow slop!

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21 VTL- voltage level for logic ‘0’ VTH- voltage level for logic ‘1’

22 REQ M V TH V TL

23 REQ M V TH V TL

24 VTH>VTL safe and robust behavior VTL>VTH, VTH < Vin < VTL C-element sensitive to noise

25 Assumption: VTH<VTL

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38 V TH V TL REQ M REQ L Oscillations when V TH < V TL

39 V TH V TL REQ M REQ L No Oscillations when V TH ＞ V TL

40 C2 Feedback circuit Feedback circuit reveal

41 Spurious Ring oscillator  X input is slow slope  X at transient voltage point so that both Pmos and Nmos are opened  Obtained effective ring oscillator

42 ≠

43 Improve digital models:  Enhance digital level transition model  Account for the analog behavior of C-element  Complex digital model far from QDI model  Bounded transition time model

44  Each node x is extended by delayed nodes x p and x n  x p feeds p–transistor, x n feeds n–transistor  Assignment x=X considered to be in progress when x p ≠ x n  Extra transition on y can occur when x enables both N and P transistors Approach Ι – model semantics REQ M REQ R ACK R

45 Safety assumption Event following x p ↓ by a slew-time occurs before the event following x p ↓ by a feedback delay a ↑ should occur after x n ↓ Approach Ι - Slew rates and feedback delay

46 Failure can occur if the length of the slew-time of x ↓ is longer than the feedback delay from x p ↓ back to a : Approach Ι – Failure condition Unsafe event

47 Bound transition time (i.e. slew-time) Insert this limitation to digital model Approach Ι – solution

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49 Targeted for small area Targeted for low power design

50 Simulating methodology VTH,VTL  VTH - minimal input voltage required to cross VDD/2 on the output (with a rising edge)  VTL - maximal input voltage required to cross VDD/2 on the output (with a falling edge) Given fast transition applied to the C-element input, compute  Output transition times  Bit flip energies

51 Initial transistor sizing The input stage is correctly sized Keeper sized to have a standard robustness to noise (comparable to the standard cell library latches). Weak feedback inverter sized to have bit-flip with a reasonable energy The fb scale ratio is defined as the feedback transistor width scaling ratio applied to the initial width of feedback transistor

52 Process flavor

53 ST 130nm HS VDD = 1.2V Energy cost = 5.0% Delay cost = 4.0% Method #1: Keeper transistor rescaling Correct operation

54 ST 130nm HS VDD = 1.2V Energy cost = 5.0% Delay cost = 4.0% Method #1: Keeper transistor rescaling Need to find optimal trade-off for power-noise Power increases drastically

55 Noise margin doesn’t depend on supply voltages

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57 ST 130nm HS VDD = 1.2V Energy cost = 5.9% Delay cost = 8.4%

58 ST 130nm HS VDD = 1.2V Energy cost = 5.9% Delay cost = 8.4%

59 Noise margin improves as voltages decreases

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61 ST 130nm HS VDD = 1.2V Energy cost = N/A Delay cost = N/A Sensitive to noise for all values of fb scale !

62 Noise margin improves as voltages decreases

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64 Minimal scaling factor Vdd=1.2V

65 Vdd reduction

66 Energy safety cost In fJoule

67 Propagation delay safety cost In ps

68 Layout example Weak feedback C-element layout W can be increased without area growth

69  VTH<VTL

70  VTH<VTL

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73 Conclusions Studied sensitivity of C-element to slow slopes Explained direction how to include slow slopes limitation in digital model Developed methodology to design slope insensitive C-elements  Resizing  VDD reduction Quasi-Delay and Slope Insensitivity methodology  New class of robust circuit to slow slopes  QDI assumption at digital level  Slope insensitivity at analog

74 References Delay insensitivity does not mean slope insensitivity! Florent Ouchet, Katell Morin-Allory, Laurent Fesquet, 2010 IEEE Symposium on Asynchronous Circuits and Systems K. van Berkel, “Beware the isochronic fork,” Integration, the VLSI Journal, vol. 13, pp. 103–128, 1992 K. Papadantonakis, “Design rules for non-atomic implementations of production rule set,” California Institute of Technology, Tech. Rep., 2005 D. Deschacht, C. Dabrin, and D. Auvergne, “Delay propagation effectin transistor gates,” IEEE Journal of Solid-State Circuits, vol. 31, Issue:8, pp. 1184–1189, August 1996