Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University RISC Pipeline See: P&H Chapter 4.6

2 A Processor alu PC imm memory d in d out addr target offset cmp control =? new pc register file inst extend +4

3 Write- Back Memory Instruction Fetch Execute p Instruction Decode register file control A Processor alu imm memory d in d out addr inst PC memory compute jump/branch targets new pc +4 extend

4 Basic Pipeline Five stage “RISC” load-store architecture 1.Instruction fetch (IF) –get instruction from memory, increment PC 2.Instruction Decode (ID) –translate opcode into control signals and read registers 3.Execute (EX) –perform ALU operation, compute jump/branch targets 4.Memory (MEM) –access memory if needed 5.Writeback (WB) –update register file Slides thanks to Sally McKee & Kavita Bala

5 Pipelined Implementation Break instructions across multiple clock cycles (five, in this case) Design a separate stage for the execution performed during each clock cycle Add pipeline registers to isolate signals between different stages

6 Write- Back Memory Instruction Fetch Execute Instruction Decode extend register file control Pipelined Processor alu memory d in d out addr PC memory new pc inst IF/ID ID/EXEX/MEMMEM/WB imm B A ctrl B DD M compute jump/branch targets +4

7 IF Stage 1: Instruction Fetch Fetch a new instruction every cycle Current PC is index to instruction memory Increment the PC at end of cycle (assume no branches for now) Write values of interest to pipeline register (IF/ID) Instruction bits (for later decoding) PC+4 (for later computing branch targets)

8 IF PC instruction memory new pc inst addrmc 00 = read word 1 IF/ID WE 1 Rest of pipeline +4 PC+4 pcsel pcreg pcrel pcabs

9 ID Stage 2: Instruction Decode On every cycle: Read IF/ID pipeline register to get instruction bits Decode instruction, generate control signals Read from register file Write values of interest to pipeline register (ID/EX) Control information, Rd index, immediates, offsets, … Contents of Ra, Rb PC+4 (for computing branch targets later)

10 ID ctrl ID/EX Rest of pipeline PC+4 inst IF/ID PC+4 Stage 1: Instruction Fetch register file WE Rd Ra Rb D B A B A extend imm decode result dest

11 EX Stage 3: Execute On every cycle: Read ID/EX pipeline register to get values and control bits Perform ALU operation Compute targets (PC+4+offset, etc.) in case this is a branch Decide if jump/branch should be taken Write values of interest to pipeline register (EX/MEM) Control information, Rd index, … Result of ALU operation Value in case this is a memory store instruction

12 Stage 2: Instruction Decode pcrel pcabs EX ctrl EX/MEM Rest of pipeline B D ctrl ID/EX PC+4 B A alu + || branch? imm pcsel pcreg

13 MEM Stage 4: Memory On every cycle: Read EX/MEM pipeline register to get values and control bits Perform memory load/store if needed –address is ALU result Write values of interest to pipeline register (MEM/WB) Control information, Rd index, … Result of memory operation Pass result of ALU operation

14 MEM ctrl MEM/WB Rest of pipeline Stage 3: Execute M D ctrl EX/MEM B D memory d in d out addr mc

15 WB Stage 5: Write-back On every cycle: Read MEM/WB pipeline register to get values and control bits Select value and write to register file

16 WB Stage 4: Memory ctrl MEM/WB M D result dest

17 IF/ID +4 ID/EXEX/MEMMEM/WB mem d in d out addr inst PC+4 OP B A Rd B D M D PC+4 imm OP Rd OP Rd PC inst mem Rd RaRb D B A

18 Example add r3, r1, r2; nand r6, r4, r5; lw r4, 20(r2); add r5, r2, r5; sw r7, 12(r3);

19 0:add 1:nand 2:lw 3:add 4:sw r0 r1 r2 r3 r4 r5 r6 r IF/ID +4 ID/EXEX/MEMMEM/WB mem d in d out addr inst PC+4 OP B A Rd B D M D PC+4 imm OP Rd OP Rd PC inst mem 77 add r3, r1, r2nand r6, r4, r5 add r3, r1, r2lw r4, 20(r2) nand r6, r4, r5 add r3, r1, r2add r5, r2, r5 lw r4, 20(r2) nand r6, r4, r5 add r3, r1, r2sw r7, 12(r3) add r5, r2, r5 lw r4, 20(r2) nand r6, r4, r5 add r3, r1, r2sw r7, 12(r3) add r5, r2, r5 lw r4, 20(r2) nand r6, r4, r5sw r7, 12(r3) add r5, r2, r5 lw r4, 20(r2)sw r7, 12(r3) add r5, r2, r5sw r7, 12(r3) Rd RaRb D B A

20 Time Graphs add nand lw add sw Clock cycle Latency: Throughput: Concurrency: CPI = IFIDEX MEM WB IFIDEX MEM WB IFIDEX MEM WB IFIDEX MEM WB IFIDEX MEM WB

21 Pipelining Recap Powerful technique for masking latencies Logically, instructions execute one at a time Physically, instructions execute in parallel –Instruction level parallelism Abstraction promotes decoupling Interface (ISA) vs. implementation (Pipeline)