Addition (2). Outline Full Adder 3-Bit Adder 2’s Complement Subtraction.

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Presentation transcript:

Addition (2)

Outline Full Adder 3-Bit Adder 2’s Complement Subtraction

A Half Adder A half adder is useful for adding LSB.

Limitation of a Half Adder A half-adder does not account for carry-in.

Derivation of the Sum Bit (∑) of a Full Adder C in ∑ half BA∑ full A+B can be derived from the ∑ half of the half adder The sum of Cin and ∑ full can be derived from an XOR gate! Perhaps this suggests that I need another half adder!

Derivation of the Carryout Bit of a Full Adder Since the C o bit in a half adder is generated by an AND gate, let’s AND ∑HA and C in and see what we get!

Derivation of the C o bit of a Full Adder C in∙ ∑ half C in ∑ half C o,half BAC o of the full adder C in∙ ∑ half generates partially correct Co. So far, we have not used information from the output of the half adder. So let’s use C o,half in the full adder circuit….

Truth Table of C o of a Full Adder C in BACoCo Identical to ∑ of a Half Adder Use a Half Adder with C in and ∑ HA to generate C o

Schematic of a Full Adder

Derivation of the Sum Bit (∑) of a Full Adder C in BA∑ full

Derivation of the C o bit of a Full Adder C in BAC o of the full adder

A 3 bit parallel adder

Since it is only possible to show magnitude with a binary number, the sign (+) or (-) is shown by adding an extra “sign” bit. –A sign bit of 0 indicates a positive number. –A sign bit of 1 indicates a negative number.