Verilog Tutorial. Outline Numbers(A.2.7) Vectors in Verilog (Section 4.1.7) Four value logic (Section 4.2.1) Comments and White Space (A.2.2) Test Methodology.

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Presentation transcript:

Verilog Tutorial

Outline Numbers(A.2.7) Vectors in Verilog (Section 4.1.7) Four value logic (Section 4.2.1) Comments and White Space (A.2.2) Test Methodology (Section 4.2.2) Propagation Delay (Section 4.3)

Number Format N’Bvalue – N is the size in bits If the size is not known, the number is assumed to have as many bits as the expression in which it is being used. Zeros are automatically padded on the front to bring it up to full size. – B is the base ‘b for binary (base 2) ‘o for octal (base 8) ‘d for decimal (base 10) ‘h for hexadecimal (base 16) If the base is omitted, the base defaults to decimal – value gives the value

Numbers 3’b101 – 3 bits, binary, 101 ‘b11 – 000…0011 8’b11 – ’hAB –

Vector in Verilog A vector in Verilog is denoted by square brackets, enclosing a contiguous range of bits. – e.g. sum[3:0] – The leftmost index in the bit range is the most significant bit – The rightmost index is the least significant bit

A Vector Example vect_word[7:0]= – vect_word[2]=1 – vect_word[3:0]=0100 ↔4 – vect_word[5:1]=00010 ↔2

Four-Value Logic 0 1 X – Represents a condition of ambiguity – X happens when a net is driven by two primitives that have opposing output values Z – Three state primitives produce an output value of Z when they are not enabled. Great care must be taken to ensure that a bus does not have contending drivers active at the same time.

Modeling Tip A verilog simulator assigns an initial value of z to all nets, which then inherit the value of their drivers. A simulator assigns an initial value of x to variables that have type reg.

Example

Comments A pair of slashes – // comment – Forms a comment from the text that follows it on the same line /* */ – /* comment */

Test Methodology Organization – Stimulus Generator – UUT – Response Monitor

A Sample Test Bench

Output

Propagation Delay Physical logic gates have a propagation delay between the time that an input changes and the time that the output responds to the change. The primitives in verilog have a default propagation delay of 0. Use 0 delay to verify functionality of a model quickly. Use a unit delay to expose the time sequence of signal activity, which can be masked by a 0-delay simulation Circuit designers do not attempt to create accurate gate level timing model of a circuit by manual methods. Instead, they rely on a synthesis tool to implement a design that will satisfy timing constraints.

Add Propagation Delay