-Alan Nelson -Andy Kruger -Dongpu Jin

 CPU is one of the most important and complicated parts of a computer.  We are going to design, implement and test a pipelined processor.

 VHDL:

 Program Counter:  16 bits D-FF  Gives the address of current instruction.

 Next instruction?  pc_src decides next instruction address.

 Control single and corresponding funcitons:

 Instruction memory:  Contain program “mif” file.  Output instruction base on the input address.

 Register file:  Extra output pins for debugging.

 Write to register:  Write back value.  Ground.  imm (load imm).  jal, bal.

 Sign-Extension:  Extend imm part of D-type instruction from 7 bits to 16 bits.

 ALU:  ALU_src determine operand of ALU.  ALUControl determine which operation it does (add, sub, AND, OR, XOR, SLL, SRL).

 Data Memory:  ALU result determine address.  Register second output goes to MEM(sw).

 Write back to register:  Select either data from memory or ALU result been written back.

 We used D-FF to store:  Two outputs from register.  imm part of instruction.  All the control signal from control except pc_src.

 Hazard Detect Unit:  When register write enable is high and write select is same as read select, want to forward WB data direct to ALU instead from register

 Better understanding how CPU works.  Better understanding how software and hardware interact.  Learned working as a team to carry out a complex design task.

 Demonstration next.