PROFIT The Changing Roles of Verification and Test in the Late-Silicon Era Tim Cheng University of California, Santa Barbara Sanya, China December 22, 2009

PROFIT

3 Shifting Focus of Design Challenges* *source: Intel

PROFIT Harder to Produce Working Chips First-silicon success rate has been dropping Yield has been dropping for volume production and takes longer to ramp up the yield “Better than worst-case” design results in failures w/o defects – adding more burden on testing Source: IBS 2007 Prob. of need for design re-spin

PROFIT Harder to Produce Working Chips First-silicon success rate has been dropping Yield has been dropping for volume production and takes longer to ramp up the yield “Better than worst-case” design results in failures w/o defects – adding more burden on testing Every design will still have bugs after tapeout and even after deployment, and For every chip manufactured, some transistors are outside spec range/non-functional, and some encounter early-life/in-field failures Eventually,

PROFIT Chip Correctness – From Design Verification to Lifetime Resiliency

PROFIT Post-Si Validation Cost Trend * SourceL John Barton, Intel: Invited talk at GSRC

PROFIT Dedicated Resource for Each Quality Assurance Function Too Costly and Wasteful

PROFIT Reusing On-Chip Functional Resources for Quality Assurance Functions Increasing the use of software-solution/system resources for detecting hardware failures Using on-chip communication and control infrastructure for test delivery and access Using cores to test each other ….. 9

PROFIT Sharing DfX Circuitry for Multiple Quality Assurance Functions Generalize DfD ckt for runtime validation Extend validation monitors for on-line testing Reuse off-line calibration circuitry for in-field online tuning Share off-line BIST and on-line checking circuitry Reuse sensors for early-life failure/wearout detection to sense silicon data for silicon validation and manufacturing testing

PROFIT Time-Multiplexed On-Line Checking (TMOC) for Cost-Sensitive Applications [ATS’08] Online checker implemented in embedded FPGA Checking one block at a time in round-robin fashion Not interrupting normal operation Case Study: An H.264 Decoder design –Checkers: duplication+comparison –Checker fabrics: eFPGA –Significant area and power o/h reductions

PROFIT Video and Document: Demo: TMOC on a Chip

PROFIT Sharing TMOC With Time-Multiplexed Assertion Checking (TMAC) TMOC infrastructure can be used for HW assertion checking as well – checking sub-blocks in round-robin fashion without interrupting normal operation Using coverage metrics to guide selection of assertions for hw implementation Adjustable area/power overheads and coverage/detection latency tradeoffs

PROFIT Digital-Assisted Analog Design Style Receiving Broad Acceptance Digital Calibration: Digitally-calibrated ADCs & RF transceivers –Goal: Linearity enhancement, mismatch compensation Digital Adaptation: Adaptive equalizer in high-speed serial links –Goal: Adapt to different operational environments Digitally-Intensive Design: All-digital PLL Testing is conducted after calibration/adaptation

PROFIT 15 Utilizing Digital Processing Unit for Post-Silicon Validation & Test Examples BIST for all-digital PLL (Staszewski et. al., TCAS-II 07) VCO frequency characterization (Demmerle, ITC06) Testable adaptive equalizer (Lin & Cheng, ITC06, Abbas et al, DATE10) Testable RF image-reject receiver (Chang & Cheng, ATS08) Pipelined ADC calibration/testing (Chang et al., ISQED09, VTS09) Analog path observability Analog path controllability 15

PROFIT Example: 3D Die-Stacking CMOS Image Sensor Architecture Every ADC processes signals from a X*Y CIS block An ISP processes signals from several ADCs Stacking CIS to ADC array stacking –Face-to-Face ADC to ISP array stacking –Through Silicon Via (TSV)

PROFIT Results of an ADC/TSV failure in 3D CIS

PROFIT Proposed Pixel-Interleaving Design Improves Error Tolerance Capability* Alter CIS output connections: outputs of nearby sensors are connected to different ADCs –Utilize de-noise schemes to achieve error tolerance Suggest to interleave only the columns, not rows –To conform to current column & row decoding scheme * Joint work of UCSB and ITRI * Ref: 3D Workshop at DATE 2010

PROFIT Error Tolerance for 3D CIS  Pixel-Interleaving + De-noise Denoise Scheme –Average the values of two nearby, same- color, different column pixels –Example: G2 = (G1+G3)/2 Error tolerant capability: At most one bad pixel within 3 nearby, same-color pixels

PROFIT Cost of Pixel-Interleaving Wiring network: at column decoder output and at column output Data rearrangement at the ISP

PROFIT Pixel-Interleaving 3D CIS Image Quality under different N PSNR = 23.33dB M =64, N = 1 PSNR = 49.39dB PSNR = 23.89dB M =64, N = 2M =64, N = 3

PROFIT Interleaving helps maintain image quality and improvement saturates after certain N One defective ADC, results of 24 Benchmark Images, M=32 Ref: Chang et al, 3D Workshop at DATE 2010

PROFIT Other New Challenges (and Research Opportunities) Verification, validation, and test for error-resilient chips/systems Coverage metrics for post-Si and system validation [Lisherness and Cheng, HLDVT 2009] –Measure of observability Ignored by many functional metrics –High-level compatibility Efficient large-scale simulation Support TLM and ad-hoc functional models Support HLS design

PROFIT What is Flexible Electronics Thin-film, light-weight, and low-cost Bendable, durable, and large-area Flexible substrates –Plastics and metal foils –Non-photolithography manufacturing Ink-jet printing Reel-to-reel imprinting [1] [2] [1] Roll-to-roll process, PolyIC; [2] Ink-jet printed electronics, Phillips

PROFIT Applications –Non-destructive structure detectors –Flexible solar cells –Flexible displays –Biometrics — Lab-on-Chip –Wearable electronics and displays Applications of Flexible Electronics © PolyIC © Univ. Tokyo © Seiko Epson © Univ. Tokyo © PolyIC year

PROFIT 26 Key Difference with CMOS Si MOSFETA-Si:H TFTOrganic TFTOxide TFT Process Temperature 1000 °C250 °CRoom Temp.150 °C Process Technology Photo- lithography Roll-to-Roll / Ink-Jet RF Sputtering Min. Length<= 65 nm10 μm50 μm10 μm Substrate Si Wafer Glass /Plastic Plastic/ Metal Foil Glass /Plastic Device TypeN- & P-typeN-typeP-typeN-type Mobility1500 cm 2 /V-s1 cm 2 /V-s0.5 cm 2 /V-s> 10 cm 2 /V-s Cost/AreaHighMediumLow LifetimeYearsMonthsWeeksYears

PROFIT Key Reliability Challenges Electrical degradation (A-Si TFT) Prolonged bias-stress on TFTs changes their properties and varies the threshold voltage (V TH ) Solutions: low-duty ratio operation, memorizing V TH with capacitors Chemical degradation (Organic TFT) Ambient oxygen and water vapor will dope the semiconducting material, change its properties, and vary V TH and I ON /I OFF ratio Solutions: material, packaging, substrate

PROFIT Research Opportunities on D&T for Reliable Flexible Electronics Reliability simulation platform* –Reliability analysis, modeling, and simulation System solutions for reliability enhancement** –Robust design for unreliable devices*** –Post-manufacturing self-test and self-tunable design –Array-based test flow Design-for-printability for roll-to-roll process –Substrate-aware physical design methodology –Self-aligned layer-to-layer patterning * Huang et al, DAC 2007 ** Huang and Cheng, Journal of Display Technologies, 2008 *** Huang et al, DATE 2010 (joint of UCSB, U of Tokyo, and ITRI)

PROFIT 29 Summary  Scaling and growing complexity challenge test and its interaction with validation and emerging issues of variability and reliability  Test should be part of a total quality assurance solution  Test solutions should become more application- and system-aware  Test should maximize sharing of DFX resources with other post-silicon tasks  Abundant research opportunities on design and test for reliable flexible electronics