Specification and Encoding of Transaction Interaction Properties Divjyot Sethi Yogesh Mahajan Sharad Malik Princeton University Hardware Verification Workshop.

Slides:



Advertisements
Similar presentations
1 Verification by Model Checking. 2 Part 1 : Motivation.
Advertisements

Functional Decompositions for Hardware Verification With a few speculations on formal methods for embedded systems Ken McMillan.
Analysis of Computer Algorithms
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study Sebastian Burckhardt Rajeev Alur Milo M. K. Martin Department of.
Tintu David Joy. Agenda Motivation Better Verification Through Symmetry-basic idea Structural Symmetry and Multiprocessor Systems Mur ϕ verification system.
Auto-Generation of Test Cases for Infinite States Reactive Systems Based on Symbolic Execution and Formula Rewriting Donghuo Chen School of Computer Science.
purpose Search : automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability.
Model Checking for an Executable Subset of UML Fei Xie 1, Vladimir Levin 2, and James C. Browne 1 1 Dept. of Computer Sciences, UT at Austin 2 Bell Laboratories,
Give qualifications of instructors: DAP
Presenter: PCLee VLSI Design, Automatic and Test, (VLSI-TSA-DAT).
Transaction Based Modeling and Verification of Hardware Protocols Xiaofang Chen, Steven M. German and Ganesh Gopalakrishnan Supported in part by Intel.
Formal verification in SPIN Karthikeyan Bhargavan, Davor Obradovic CIS573, Fall 1999.
ECE 720T5 Fall 2012 Cyber-Physical Systems Rodolfo Pellizzoni.
6/14/991 Symbolic verification of systems with state machines David L. Dill Jeffrey Su Jens Skakkebaek Computer System Laboratory Stanford University.
Presenter: PCLee – This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation.
1 Formal Methods in SE Qaisar Javaid Assistant Professor Lecture 05.
Teaching MC to Undergrads. Abhik Roychoudhury National University of Singapore.
An Automata-based Approach to Testing Properties in Event Traces H. Hallal, S. Boroday, A. Ulrich, A. Petrenko Sophia Antipolis, France, May 2003.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Presenter : Yeh Chi-Tsai System-on-chip validation using UML and CWL Qiang Zhu 1, Ryosuke Oish 1, Takashi Hasegawa 2, Tsuneo Nakata 1 1 Fujitsu Laboratories.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
Modeling Software Systems Lecture 2 Book: Chapter 4.
FunState – An Internal Design Representation for Codesign A model that enables representations of different types of system components. Mixture of functional.
Symbolic Encoding of Neural Networks using Communicating Automata with Applications to Verification of Neural Network Based Controllers* Li Su, Howard.
Partial Order Reduction for Scalable Testing of SystemC TLM Designs Sudipta Kundu, University of California, San Diego Malay Ganai, NEC Laboratories America.
Software Engineering, COMP201 Slide 1 Protocol Engineering Protocol Specification using CFSM model Lecture 30.
Functional Coverage Driven Test Generation for Validation of Pipelined Processors P. Mishra and N. Dutt Proceedings of the Design, Automation and Test.
November 18, 2004 Embedded System Design Flow Arkadeb Ghosal Alessandro Pinto Daniele Gasperini Alberto Sangiovanni-Vincentelli
Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification Sudhindra Pandav Konrad Slind Ganesh Gopalakrishnan.
1 Formal Engineering of Reliable Software LASER 2004 school Tutorial, Lecture1 Natasha Sharygina Carnegie Mellon University.
Real-Time System Requirements & Design Specs Shaw - Chapters 3 & 4 Homework #2: 3.3.1, 3.4.1, Add Error states to Fig 4.1 Lecture 4/17.
Router modeling using Ptolemy Xuanming Dong and Amit Mahajan May 15, 2002 EE290N.
Transaction Based Modeling and Verification of Hardware Protocols Xiaofang Chen, Steven M. German and Ganesh Gopalakrishnan Supported in part by SRC Contract.
[ §4 : 1 ] 4. Requirements Processes II Overview 4.1Fundamentals 4.2Elicitation 4.3Specification 4.4Verification 4.5Validation Software Requirements Specification.
Formal Techniques for Verification Using SystemC By Nasir Mahmood.
Presenter : Cheng-Ta Wu Vijay D’silva, S. Ramesh Indian Institute of Technology Bombay Arcot Sowmya University of New South Wales, Sydney.
Verification technique on SA applications using Incremental Model Checking 컴퓨터학과 신영주.
ECE 720T5 Winter 2014 Cyber-Physical Systems Rodolfo Pellizzoni.
Introduction Overview Static analysis Memory analysis Kernel integrity checking Implementation and evaluation Limitations and future work Conclusions.
Benjamin Gamble. What is Time?  Can mean many different things to a computer Dynamic Equation Variable System State 2.
CS6133 Software Specification and Verification
Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in.
Requirements Capture. Four Steps of requirements capture List candidate requirements Understand system context Capture functional requirements Capture.
Computers Operating System Essentials. Operating Systems PROGRAM HARDWARE OPERATING SYSTEM.
CS5270 Lecture 41 Timed Automata I CS 5270 Lecture 4.
Controller Synthesis for Pipelined Circuits Using Uninterpreted Functions Georg Hofferek and Roderick Bloem. MEMOCODE 2011.
Architectural Point Mapping for Design Traceability Naoyasu Ubayashi and Yasutaka Kamei Kyushu University, Japan March 26, 2012 FOAL 2012 (AOSD Workshop)
Streamflow - Programming Model for Data Streaming in Scientific Workflows Chathura Herath.
Verification Driven Formal Architecture and  Architecture Modeling Sharad Malik, Yogesh Mahajan, Carven Chan, Ali Bayazit Princeton University Wei Qin.
ECE-C662 Lecture 2 Prawat Nagvajara
1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW.
Constraints Assisted Modeling and Validation Presented in CS294-5 (Spring 2007) Thomas Huining Feng Based on: [1]Constraints Assisted Modeling and Validation.
1 Distributed BDD-based Model Checking Orna Grumberg Technion, Israel Joint work with Tamir Heyman, Nili Ifergan, and Assaf Schuster CAV00, FMCAD00, CAV01,
Software Systems Verification and Validation Laboratory Assignment 4 Model checking Assignment date: Lab 4 Delivery date: Lab 4, 5.
Bounded Model Checking A. Biere, A. Cimatti, E. Clarke, Y. Zhu, Symbolic Model Checking without BDDs, TACAS’99 Presented by Daniel Choi Provable Software.
From Natural Language to LTL: Difficulties Capturing Natural Language Specification in Formal Languages for Automatic Analysis Elsa L Gunter NJIT.
1 CEN 4020 Software Engineering PPT4: Requirement analysis.
Compositional Verification for System-on-Chip Designs SRC Student Symposium Paper 16.5 Nishant Sinha Edmund Clarke Carnegie Mellon University.
Writing, Verifying and Exploiting Formal Specifications for Hardware Designs Chapter 3: Verifying a Specification Presenter: Scott Crosby.
Symbolic Model Checking of Software Nishant Sinha with Edmund Clarke, Flavio Lerda, Michael Theobald Carnegie Mellon University.
CS5270 Lecture 41 Timed Automata I CS 5270 Lecture 4.
Formal methods: Lecture
Formal verification in SPIN
Fei Li Jinjun Xiong University of Wisconsin-Madison
Yogesh Mahajan, Sharad Malik Princeton University
Model Checking for an Executable Subset of UML
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
Hongyu Zhang, Jeremy S. Bradbury, James R. Cordy, Juergen Dingel
ECE 667 Synthesis and Verification of Digital Systems
Presentation transcript:

Specification and Encoding of Transaction Interaction Properties Divjyot Sethi Yogesh Mahajan Sharad Malik Princeton University Hardware Verification Workshop Edinburgh July 15,

Gap Between Specification and Implementation Consequences for Verification Need humans to translate correctness conditions between them Incomplete, expensive, error prone Significant barrier to automation in verification. Specification Objects are units of data Concurrent computation on these objects I mplementation Objects are functional logic blocks Concurrent communication between these objects Packet HT Instr OpImmediateRsRt Frame l1l1 lnln M1M2M3 Pipeline Mapping of concurrent functions onto concurrent hardware blocks is captured by humans Drives efforts to move design and verification to levels above RTL.

3 Time Transaction Sequence Order Modeling Concurrent Computation Using Transactions Transaction is a unit of work Transactions can be concurrent Transaction sequences Permits reasoning about Individual transactions Interactions between transactions e.g. pipeline hazards T1T1 T2T2 T3T3 Shared Resource

Transaction Interaction Properties Examples – Contention Mutual exclusion – Sequencing Ordering of packets in a router Pipeline hazards – Priority Choosing among concurrent processes 4 Generally deal with ordering of individual transaction instances.

Transaction Interaction Properties in RTL Lack high-level information – Where are the instructions? Need to instrument the design to capture high-level objects – Instructions in flight Need to state the property in terms of instrumented variables Human intervention limits automation 5 Example: RAW Pipeline Hazard Easier with a transaction-level model with explicit ordering information.

Transaction- Level Model Transaction Interaction Property Synthesized RTL Automated Encoding Finite Model + Temporal Logic Property This Work Previous Work (CODES+ISSS 09) Big Picture Verified Synthesis + Model Check This

Talk Outline Motivation Modeling Transactions and Interaction Properties Encoding for Model Checking Experiments Related Work Summary 7

Transaction-Level Model Individual Transaction – Explicit start and end steps – Guarded transitions – Model as a Kripke structure Infinite array of transactions – Index value refers to specific transaction State – Local Transaction state – present step & local variables – Local variables constant after a transaction ends – Global shared state 8 i T1T1 T2T2 TiTi M1M1 Global State Local State Of T i End Step Start Step Guarded Transitions Modeled as an infinite Kripke structure Parametric, but not symmetric in i

Property Specification using Indexed Temporal Logic 9  i,j j>i  G~( read j & ~write i & F(write i )) Example: RAW hazard property i, j are transaction indices  I, P(I)   [L(I),g] General Form of property: I: Set of index variables, one for each interacting transaction P(I): Predicate on the set of indices I capturing relationship among interacting transactions  [L(I),g]: Temporal logic formula on transaction local indexed variables and global variables Indexed transaction local variables Indexed Temporal Logic Formula

Talk Outline Motivation Modeling Transactions and Interaction Properties Encoding for Model Checking Experiments Related Work Summary 10

Encoding for Model Checking 11 i T1T1 T2T2 TiTi M1M1 Global State Indexed State Infinite State Model  I, P(I)   [v(I),g] + Finite State Model LTL/CTL Formula + Model Check This Encode

Handling Infinite State 12 i T1T1 T2T2 TiTi M1M1 Global State Indexed State Infinite State Model  I, P(I)   [v(I),g] + Observation 1: Only a finite number of active transactions possible due to finite resources Finite state for active transactions S1S1 S2S2 SKSK State of active transactions User specified upper bound Independently verified

Handling Infinite State 13 i T1T1 T2T2 TiTi M1M1 Global State Indexed State Infinite State Model  I, P(I)   [v(I),g] + But, properties may refer to local variables of transactions that have ended. Observation 2: Can exploit non-determinism. Non-deterministically select |I| transactions for tracking past history. The model checker will implicitly consider all possible values. E1E1 E2E2 E |I| Local variables of selected transactions Number of interacting transactions

Encoding the Predicate 14 i T1T1 T2T2 TiTi M1M1 Global State Indexed State Infinite State Model  I, P(I)   [v(I),g] + But, predicate evaluation needs the potentially infinite index value of the interacting transactions. Observation 3: Can handle several (all?) useful predicates without explicit index value storage. Ordering Constraints P(i, j) : i > j Separation Constraints P(i, j) : i − j > m P(i, j) : i − j < m Equality Constraints: P(i, j) i = j + m Inequality constraints P(i, j) : i  j + m Predicate FSM ND_Select i ND_Select j I = {i,j}

Encoding for Model Checking 15 i T1T1 T2T2 TiTi M1M1 Global State Indexed State Infinite State Model  I, P(I)   [v(I),g] + Key Components Predicate FSM ND_Select i ND_Select j S1S1 S2S2 SKSK State of active transactions E1E1 E2E2 E |I| Local variables of ended transactions

Talk Outline Motivation Modeling Transactions and Interaction Properties Encoding for Model Checking Experiments Related Work Summary 16

Experiments Design examples – Simple router Property: Flits are processed in order – Simple processor Property: Absence of RAW hazard Input: – Designs specified using a transaction-level model – Properties specified using indexed temporal logic Output: – Synthesized SMV for finite model and LTL property – Model checked using Cadence SMV 17

Model Checking Results 18 All experiments done on Intel Core 2 Duo 2.5GHz 3 GB RAM Machine with Windows XP

Talk Outline Motivation Modeling Transactions and Interaction Properties Encoding for Model Checking Experiments Related Work Summary 19

Related Work Summary 20

Talk Outline Motivation Modeling Transactions and Interaction Properties Encoding for Model Checking Experiments Related Work Summary 21

Summary Transaction-based higher-level models enable reasoning without resorting to design instrumentation Main Contributions: – Infinite Kripke structure model for transactions with explicit indices – Indexed temporal logic for specifying transactions interactions properties – Finite encoding of design and property exploiting Finiteness of hardware resources Non-determinism in model checkers Specific ordering relationships of interacting transactions – Initial prototype demonstration 22

Related Papers Y. Mahajan, C. Chan, A. Bayazit, S. Malik, and W. Qin, “Verification driven formal architecture and microarchitecture modeling,” in MEMOCODE ’07: Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign. Washington, DC, USA: IEEE Computer Society, 2007, pp. 123–132. Y. Mahajan and S. Malik, “Automating hazard checking in transaction-level microarchitecture models,” in FMCAD ’07: Proceedings of the Formal Methods in Computer Aided Design. Washington, DC, USA: IEEE Computer Society, 2007, pp. 62–65. D. Schwartz-Narbonne, C. Chan, Y. Mahajan, and S. Malik, “Supporting RTL flow compatibility in a microarchitecture-level design framework,” in CODES+ISSS ’09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis. New York, NY, USA: ACM, 2009, pp. 343–