Setting the flip-flop The normal value of R and S is zero. S (set) = 0 R (reset) = 0 remembered value 1.

Slides:



Advertisements
Similar presentations
Truth Tables and Logic Gates. What are Logic Gates? Logic gates are components used in making logic circuits. Each gate has one or more inputs and produces.
Advertisements

Logic Gates.
Sequential Logic Circuits. Set-Reset Latch The Set-Reset latch or bistable is a simple sequential logic circuit that remembers what has happened to the.
Galen SasakiEE 260 University of Hawaii1 Building D Flip Flops Combinational circuit components D Clocked Latch: similar to a flip flop but simpler D flip.
Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.
1 Fundamentals of Computer Science Sequential Circuits.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 12 Basic (NAND) S – R Latch “Cross-Coupling” two NAND gates gives the S -R Latch:
CP208 Digital Electronics Class Lecture 11 May 13, 2009.
Latches and Flip-Flops Discussion D8.1 Section 13-9.
Latches Chapter 14 Subject: Digital System Year: 2009.
LOGIC GATES ADDERS FLIP-FLOPS REGISTERS Digital Electronics Mark Neil - Microprocessor Course 1.
Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.
1. 2 Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs.
CSE115: Introduction to Computer Science I Dr. Carl Alphonce 219 Bell Hall 1.
CSE115: Introduction to Computer Science I Dr. Carl Alphonce 219 Bell Hall 1.
CSE111: Great Ideas in Computer Science Dr. Carl Alphonce 219 Bell Hall Office hours: M-F 11:00-11:
CSE115: Introduction to Computer Science I Dr. Carl Alphonce 219 Bell Hall 1.
CSE111: Great Ideas in Computer Science Dr. Carl Alphonce 219 Bell Hall Office hours: M-F 11:00-11:
Latches Module M10.1 Section 7.1. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only.
EECC341 - Shaaban #1 Lec # 13 Winter Sequential Logic Circuits Unlike combinational logic circuits, the output of sequential logic circuits.
Spring 2002EECS150 - Lec14-seq1 Page 1 EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements) March 12, 2002 John Wawrzynek.
ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip.
Latches Section 4-2 Mano & Kime. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only.
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
Latches Lecture L8.1 Section 7.1 – Book Sect. 8.1– Handout.
Latches and Flip-Flops Discussion D4.1 Appendix J.
Memory. The logic and arithmetic circuits we’ve seen so far have no memory. They just transform input to output. Can we make circuits that remember? Memory.
TOPIC : BILBO BIST Architectures UNIT 5 : BIST and BIST Architectures Module 5.2 BIST.
Fall 2007 L16: Memory Elements LECTURE 16: Clocks Sequential circuit design The basic memory element: a latch Flip Flops.
PHY 201 (Blum)1 Other types of flip-flops and counting See Chapter 9 and 10 in Digital principles (Tokheim)
Digital Logic Design CHAPTER 5 Sequential Logic. 2 Sequential Circuits Combinational circuits – The outputs are entirely dependent on the current inputs.
In this module you will learn: What the various logic gates do. How to represent logic gates on a circuit diagram. The truth tables for the logic gates.
Flip Flops. Clock Signal Sequential logic circuits have memory Output is a function of input and present state Sequential circuits are synchronized by.
BY: TRAVIS HOOVER 2/22/2011 CS 147 DR. LEE JK flip-flops.
Block Diagram of 4518 Dual BCD Counter The 4518 Dual BCD Counter has two BCD counters. Each counter is similar to the other. Each counter has a master.
Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics.
Components used in the the Project J-K Flip Flop Switch Power Alternator 7-Segment Display Coded Decimal (BCD) Display.
1 Sequential Circuit Latch & Flip-flop. 2 Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK.
Circuit, State Diagram, State Table
TODAY YOU ARE LEARNING to explain why data is represented in computer systems in binary form 2. to understand and produce simple logic diagrams.
CSE115 / CSE503 Introduction to Computer Science I Dr. Carl Alphonce 343 Davis Hall 1.
What is an And Gate? It is a digital circuit that produce logical operations The logical operations are call Boolean logical Boolean operation consist.
 In studying digital integrated circuits, one must start with the simplest group of circuit, the SSIs or Small Scale Integrated Circuits. Since these.
D Latch Delay (D) latch:a) logic symbolb) NAND implementationc) NOR implementation.
Unit 11 Latches and Flip-Flops Fundamentals of Logic Design By Roth and Kinney.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
Linear Algebra. Circuits The circuits in computers and other input devices have inputs, each of which is either a 0 or 1, the output is also 0s and 1s.
9/15/09 - L24 Other FF TypesCopyright Joanne DeGroat, ECE, OSU1 Other FF Types.
SEQUENTIAL LOGIC By Tom Fitch. Types of Circuits Combinational: Gates Combinational: Gates Sequential: Flip-Flops Sequential: Flip-Flops.
CSE115: Introduction to Computer Science I Dr. Carl Alphonce 219 Bell Hall
Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain.
© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.
Logic Gates. AND gate Produces an output only if both inputs are on Input AInput BOutput (Q) Q=
Boolean and Sequential Logic Last week – Basic Gates AND OR NOT NOR XOR NAND.
Sequential Logic Computer Organization II 1 © McQuain A clock is a free-running signal with a cycle time. A clock may be either high or.
Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.
Sequential Circuit Latch & Flip-flop. Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK flip-flop.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
AND Gate Inputs Output Input A (Switch) Input B (Switch) Output Y (Lamp) 0 (Open) 0 (OFF) A B Lamp.
CO5023 Building Circuits from Truth Tables. Build the following… Let’s say we want a circuit which acts as described by the following truth table: We.
CS151 Introduction to Digital Design Chapter 5: Sequential Circuits 5-1 : Sequential Circuit Definition 5-2: Latches 1Created by: Ms.Amany AlSaleh.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
1. 2 Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs.
FLIP FLOPS Binary unit capable of storing one bit – 0 or 1
KS4 Electricity – Electronic systems
KS4 Electricity – Electronic systems
More about DesignWorks
Digital Logic.
KS4 Electricity – Electronic systems
FLIP-FLOP. The basic memory circuit is known as Flip-flop. OR It is a bistable sequential circuit which has two stable state (set & reset) and can be.
Presentation transcript:

Setting the flip-flop The normal value of R and S is zero. S (set) = 0 R (reset) = 0 remembered value 1

Setting the flip-flop To store 1 in the flip-flop, we “raise” S to 1… S (set) = 1 R (reset) = 0 remembered value 2

Setting the flip-flop …which makes the output of the OR gate 1. S (set) = 1 R (reset) = 0 remembered value 3 1

Setting the flip-flop The NOT gate inverts this 1 value to 0, which becomes the second input to the upper OR gate. S (set) = 1 R (reset) = 0 remembered value

Setting the flip-flop Since both inputs of the upper OR gate are zero, its output is zero. S (set) = 1 R (reset) = 0 remembered value

Setting the flip-flop The NOT gate inverts this 0 to a 1; this value becomes the second input to the bottom OR. S (set) = 1 R (reset) = 0 remembered value

Setting the flip-flop Because the output of the bottom OR gate will now stay at 1, we can lower S to zero, and the circuit will stay in a stable state, with 1 as the remembered value! S (set) = 0 R (reset) = 0 remembered value Resetting the flip-flop Resetting the remembered value to zero is similar, except we raise, then lower, the value on R.