P ROCESSING WHILE ROUTING : A NETWORK - ON - CHIP - BASED PARALLEL SYSTEM S.R. Fernandes 1 B.C. Oliveira 2 M. Costa 2 I.S. Silva 2 Computers & Digital Techniques, IET,2009 Reporter: 陳健豪

OUTLINE Introduction Related works IPNoSys architecture Results Conclusions

I NTRODUCTION Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. Bus-based design remains useful while the number of cores in the processor is kept to a limit. More powerful interconnections, such as network-on-chip(NoC).

I NTRODUCTION NoC requires more chip area and more power. This paper proposes IPNoSys system, where the routers are also responsible for the execution of operations,besides the routing process.

R ELATED WORKS NoC

IPN O S YS ARCHITECTURE The NoC is not only interconnection mechanism but also becomes an active element in the execution of applications. square 2D mesh XY routing policy virtual-cut-through (VCT) and wormhole switching scheme virtual channel credit-based control flow distributed arbitration and input buffering

IPN O S YS ARCHITECTURE

An arithmetic logic unit (ALU) allowing the router to perform the most common logic- arithmetic operations usually found in applications. Routing packets and processing,being called routing and processing unit (RPU). The memory modules are accessed by memory access cores (MAC).

IPN O S YS ARCHITECTURE

spiral complement routing algorithm:

IPN O S YS ARCHITECTURE Deadlock treatment:

The number of virtual channels is the number of times that the packet should pass through the same physical channel in the same direction. In our case the maximum is three times (Fig. 3) Thus, the IPNoSys system treats the deadlock through a solution called local execution

IPN O S YS ARCHITECTURE Packet format

IPN O S YS ARCHITECTURE Routing and processing unit (RPU)

IPN O S YS ARCHITECTURE

Memory access core The MACs placed in the corners are responsible for reading the packets from memory and to injecting them into the NoC,

R ESULTS implemented in cycle-accurate SystemC Different NoC dimensions Three simulation cases Simple counter DCT RLE

R ESULTS Simple counter sequential and a parallel execution

IPNoSys system allowed to reduce the maximum number of performed instructions around 80% comparing the sequential and parallel execution

R ESULTS DCT The 2D-DCT is largely used in compression process of images.

The DCT application has much data dependencies,which is the worst case in ILP.

Required memory for IPNoSys is slightly increased with more parallelism because of the rise of the communication.

R ESULTS RLE RLE is suited for compressing any type of data regardless of its information content. For example, an uncompressed string formed by 15‘A’characters would normally require 15 bytes to store:AAAAAAAAAAAAAAA.

It means the number of packets decrease,on average, at the end of its execution.

D ETAILED COMPARISON (STORM X IPN O S YS ) STORM instances with one, two, four or 15 SPARC V8 processors 2D-mesh NoC two, three, five and 16 routers,respectively cache coherent directory-based MP-SoC platform XY routing scheme

C ONCLUSIONS This paper presented an innovative NoC-based architecture that does not use traditional processors, IPNoSys. Architecture’s execution capability independent of the number of application instructions and NoC dimensions. In DCT,the execution time in the IPNoSys is 3.5 times smaller than the STORM best case that shows the efficiency of the parallelism in this system. In RLE,the IPNoSys performance also was better than STORM.