CSE 490/590, Spring 2011 CSE 490/590 Computer Architecture ILP I Steve Ko Computer Sciences and Engineering University at Buffalo

CSE 490/590, Spring Last time… Scoreboard –Data structure that keeps track of dependencies among instructions In-order limitations –Out-of-order alone cannot solve Register renaming –Overcoming the restriction caused by the # of registers

CSE 490/590, Spring Instruction-level Parallelism via Renaming latency 1LDF2, 34(R2)1 2LDF4,45(R3)long 3MULTDF6,F4,F23 4SUBDF8,F2,F21 5DIVDF4’,F2,F84 6ADDDF10,F6,F4’1 In-order: 1 (2,1) Out-of-order: 1 (2,1) (3,5) X Any antidependence can be eliminated by renaming. (renaming  additional storage) Can it be done in hardware? yes!

CSE 490/590, Spring Register Renaming Decode does register renaming and adds instructions to the issue stage reorder buffer (ROB)  renaming makes WAR or WAW hazards impossible Any instruction in ROB whose RAW hazards have been satisfied can be dispatched.  Out-of-order or dataflow execution IFIDWB ALUMem Fadd Fmul Issue

CSE 490/590, Spring Dataflow Execution Instruction slot is candidate for execution when: It holds a valid instruction (“use” bit is set) It has not already started execution (“exec” bit is clear) Both operands are available (p1 and p2 are set) Reorder buffer t1t2...tnt1t2...tn ptr 2 next to deallocate ptr 1 next available Ins# use exec op p1 src1 p2 src2

CSE 490/590, Spring Renaming & Out-of-order Issue An example When are tags in sources replaced by data? When can a name be reused? 1LDF2, 34(R2) 2LDF4,45(R3) 3MULTDF6,F4,F2 4SUBDF8,F2,F2 5DIVDF4,F2,F8 6ADDDF10,F6,F4 Renaming tableReorder buffer Ins# use exec op p1 src1 p2 src2 t1t2t3t4t5..t1t2t3t4t5.. data / t i p data F1 F2 F3 F4 F5 F6 F7 F8 Whenever an FU produces data Whenever an instruction completes t LD t LD DIV 1 v1 0 t SUB 1 v1 1 v1 t MUL 0 t2 1 v1 t3 t5 v LD SUB 1 v1 1 v1 4 0 v DIV 1 v1 1 v LD MUL 1 v2 1 v1

CSE 490/590, Spring Data-Driven Execution Renaming table & reg file Reorder buffer Load Unit FU Store Unit Ins# use exec op p1 src1 p2 src2 t1t2..tnt1t2..tn Instruction template (i.e., tag t) is allocated by the Decode stage, which also associates tag with register in regfile When an instruction completes, its tag is deallocated Replacing the tag by its value is an expensive operation

CSE 490/590, Spring Simplifying Allocation/Deallocation Instruction buffer is managed circularly “exec” bit is set when instruction begins execution When an instruction completes its “use” bit is marked free ptr 2 is incremented only if the “use” bit is marked free Reorder buffer t1t2...tnt1t2...tn ptr 2 next to deallocate ptr 1 next available Ins# use exec op p1 src1 p2 src2

CSE 490/590, Spring IBM 360/91 Floating-Point Unit R. M. Tomasulo, 1967 Mult load buffers (from memory) Adder Floating- Point Reg store buffers (to memory)... instructions Common bus ensures that data is made available immediately to all the instructions waiting for it. Match tag, if equal, copy value & set presence “p”. Distribute instruction templates by functional units ptag/datap p p p p p p p p p p p 2 p p p p p p p p p p

CSE 490/590, Spring Effectiveness? Renaming and Out-of-order execution was first implemented in 1969 in IBM 360/91 but did not show up in the subsequent models until mid- Nineties. Why ? Reasons 1. Effective on a very small class of programs 2. Memory latency a much bigger problem 3. Exceptions not precise! One more problem needed to be solved Control transfers

CSE 490/590, Spring CSE 490/590 Administrivia No office hours this week –Appointment via if needed –Project-related questions  fastest: Safwan or Jangyoung Guest Lecture by Prof. Kris Schindler on Wed Guest lecture by Prof. Tevfik Kosar on Fri

CSE 490/590, Spring Precise Interrupts It must appear as if an interrupt is taken between two instructions (say I i and I i+1 ) the effect of all instructions up to and including I i is totally complete no effect of any instruction after I i has taken place The interrupt handler either aborts the program or restarts it at I i+1.

CSE 490/590, Spring Effect on Interrupts Out-of-order Completion I 1 DIVDf6, f6,f4 I 2 LDf2,45(r3) I 3 MULTDf0,f2,f4 I 4 DIVDf8,f6,f2 I 5 SUBDf10,f0,f6 I 6 ADDDf6,f8,f2 out-of-order comp restore f2 restore f10 Consider interrupts Precise interrupts are difficult to implement at high speed - want to start execution of later instructions before exception checks finished on earlier instructions

CSE 490/590, Spring Exception Handling (In-Order Five-Stage Pipeline) Hold exception flags in pipeline until commit point (M stage) Exceptions in earlier pipe stages override later exceptions Inject external interrupts at commit point (override others) If exception at commit: update Cause and EPC registers, kill all stages, inject handler PC into fetch stage Asynchronous Interrupts Exc D PC D PC Inst. Mem D Decode EM Data Mem W + Exc E PC E Exc M PC M Cause EPC Kill D Stage Kill F Stage Kill E Stage Illegal Opcode Overflow Data Addr Except PC Address Exceptions Kill Writeback Select Handler PC Commit Point

CSE 490/590, Spring Fetch: Instruction bits retrieved from cache. Phases of Instruction Execution I-cache Fetch Buffer Issue Buffer Func. Units Arch. State Execute: Instructions and operands sent to execution units. When execution completes, all results and exception flags are available. Decode: Instructions placed in appropriate issue (aka “dispatch”) stage buffer Result Buffer Commit: Instruction irrevocably updates architectural state (aka “graduation” or “completion”). PC

CSE 490/590, Spring Acknowledgements These slides heavily contain material developed and copyright by –Krste Asanovic (MIT/UCB) –David Patterson (UCB) And also by: –Arvind (MIT) –Joel Emer (Intel/MIT) –James Hoe (CMU) –John Kubiatowicz (UCB) MIT material derived from course UCB material derived from course CS252