Half Adder ( / ) Structural description: Data flow description:

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Dept. of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C

Half Adder ( / ) Structural description: Data flow description: module Add_half(sum, c_out, a ,b); input a, b; output sum, c_out; wire c_out_bar; xor x1(sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule module Add_half(sum, c_out, a ,b); input a, b; output sum, c_out; assign sum = a^b assign c_out = ~(a&b); endmodule

Half Adder ( / ) Data flow description: assign: continuous assignment module Add_half(sum, c_out, a ,b); input a, b; output sum, c_out; assign {c_out, sum} = a + b; endmodule assign: continuous assignment

Half Adder ( / ) Behavior description: module Add_half(sum, c_out, a ,b); input a, b; output sum, c_out; reg sum, c_out; always@(a or b) begin {c_out, sum} = a + b; end endmodule

Full Adder ( / ) Data flow description: Behavior description: module Add_full(sum, c_out, a ,b, c_in); input a, b, c_in; output sum, c_out; reg sum, c_out; assign {c_out, sum} = a + b + c_in; endmodule module Add_full(sum, c_out, a ,b, c_in); input a, b, c_in; output sum, c_out; reg sum, c_out; always@(a or b or c_in) begin {c_out, sum} = a + b + c_in; end endmodule

Hierarchical Description of Circuit module Add_full(sum, c_out, a ,b); input a, b; output sum, c_out; wire c_in3, c_in2, c_in1; Add_half G1(sum[0], c_in1, a[0], b[0]); Add_full G2(sum[0], c_in2, a[1], b[1], c_in1); Add_full G3(sum[0], c_in3, a[2], b[2], c_in2); Add_full G4(sum[0], c_out, a[3], b[3], c_in3); endmodule Ripple-Carry Adder: c_in3 c_in2 c_in1 half

Full Adder with high level description module Add_4bit(sum, c_out, a ,b); input [3:0] a, b; output [3:0] sum; output c_out; assign {c_out, sum} = a + b; endmodule The synthesized circuit is dependent on the tool you use (might be ripple-carry Adder or other Adders).

If-Else Statements ( / )

If-Else Statements ( / )

Case Statements ( / )

Case Statements ( / )

Decoder with Case Statements