Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 211 Lecture 21 I DDQ Current Testing n Definition n Faults detected by I DDQ tests n Vector generation for I DDQ tests  Full-scan  Quietest n Instrumentation difficulties n Sematech study n Limitations of I DDQ testing n Summary

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 212 Motivation n Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips  IBM wants to get 3.4 defects per million (dpm) chips (0 defects, 6  ) n Conventional way to reduce defects:  Increasing test fault coverage  Increasing burn-in coverage  Increase Electro-Static Damage awareness n New way to reduce defects:  I DDQ Testing – also useful for Failure Effect Analysis

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 213 Basic Principle of I DDQ Testing n Measure I DDQ current through V ss bus

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 214 Faults Detected by I DDQ Tests

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 215 Stuck-at Faults Detected by I DDQ Tests n Bridging faults with stuck-at fault behavior  Levi – Bridging of a logic node to V DD or V SS – few of these  Transistor gate oxide short of 1 K  to 5 K  n Floating MOSFET gate defects – do not fully turn off transistor

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 216 NAND Open Circuit Defect – Floating gate

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 217 Floating Gate Defects n Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling  Delay fault and I DDQ fault n Large open results in stuck-at fault – not detectable by I DDQ test  If V tn < V fn < V DD - | V tp | then detectable by I DDQ test

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 218 Multiple I DDQ Fault Example

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 219 Capacitive Coupling of Floating Gates n C pb – capacitance from poly to bulk n C mp – overlapped metal wire to poly n Floating gate voltage depends on capacitances and node voltages n If nFET and pFET get enough gate voltage to turn them on, then I DDQ test detects this defect n K is the transistor gain

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2110 I DDQ Current Transfer Characteristic Segura et al. – 5 defective inverter chains (1-5) with floating gate defects

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2111 Bridging Faults S 1 – S 5 Caused by absolute short (< 50  ) or higher R n Segura et al. evaluated testing of bridges with 3 CMOS inverter chain I DDQRb tests fault when R b > 50 K  or 0 R b 100 K  n Largest deviation when V in = 5 V bridged nodes at opposite logic values  

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2112 S1 I DDQ Depends on K, Rb K |I DDQ | (  A) Rb (k  )

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2113 CMOS Transistor Stuck- Open Faults n I DDQ test can sometimes detect fault  Works in practice due to body effect

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2114 Delay Faults n Most random CMOS defects cause a timing delay fault, not catastrophic failure n Many delay faults detected by I DDQ test – late switching of logic gates keeps I DDQ elevated n Delay faults not detected by I DDQ test  Resistive via fault in interconnect  Increased transistor threshold voltage fault

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2115 Leakage Faults n Gate oxide shorts cause leaks between gate & source or gate & drain n Mao and Gulati leakage fault model:  Leakage path flags: f GS, f GD, f SD, f BS, f BD, f BG G = gate, S = source, D = drain, B = bulk n Assume that short does not change logic values

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2116 Weak Faults n nFET passes logic 1 as 5 V – V tn n pFET passes logic 0 as 0 V + |V tp | n Weak fault – one device in C-switch does not turn on  Causes logic value degradation in C-switch

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2117 Paths in Circuit

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2118 Transistor Stuck-Closed Faults n Due to gate oxide short (GOS) n k = distance of short from drain n R s = short resistance n I DDQ2 current results show 3 or 4 orders of magnitude elevation

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2119 Gate Oxide Short

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2120 Logic / I DDQ Testing Zones

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2121 Fault Coverage Metrics n Conductance fault model (Malaiya & Su)  Monitor I DDQ to detect all leakage faults  Proved that stuck fault test set can be used to generate minimum leakage fault test set n Short fault coverage  Handles intra-gate bridges, but may not handle inter-gate bridges n Pseudo-stuck-at fault coverage  Voltage stuck-at fault coverage that represents internal transistor short fault coverage and hard stuck-at fault coverage

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2122 Fault Coverages for I DDQ Fault Models

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2123 Vector Selection with Full Scan -- Perry n Use voltage testing & full scan for I DDQ tests n Measure I DDQ current when voltage vector set hits internal scan boundary  Set all nodes, inputs & outputs in known state  Stop clock & apply minimum I DDQ current vector  Wait 30 ms for settling, measure I DDQ against 75  A Limit, with 1  A accuracy

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2124 Quietest Leakage Fault Detection – Mao and Gulati n Sensitize leakage fault n Detection – 2 transistor terminals with leakage must have opposite logic values, & be at driving strengths n Non-driving, high-impedance states won’t work – current cannot go through them

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2125 Weak Fault Detection – P1 (N1) Open Elevates I DDQ from 0  A to 56  A

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2126 Second Weak Fault Detection Example n Not detected unless I3 = 1

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2127 Hierarchical Vector Selection n Generate complete stuck-fault tests n Characterize each logic component – relate input/output logic values & internal states:  To leakage fault detection  To weak fault sensitization/propagation  Uses switch-level simulation n Store information in leakage & weak fault tables n Logic simulate stuck-fault tests – use tables to find faults detected by each vector  No more switch-level simulation

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2128 Leakage Fault Table n k = # component I/O pins n n = # component transistors n m = 2 k (# of input / output combinations) n m x n matrix M represents the table n Each logic state – 1 matrix row n Entry m i j = octal leakage fault information  Flags f BG f BD f BS f SD f GD f GS  Sub-entry m i j = 1 if leakage fault detected

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2129 Example Leakage Fault Table

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2130 Weak Fault Table n Weak faults:  Sensitized by input/output states of faulty component  Propagated by either faulty component input/output states or input/output states of components driven by node with weak fault n Use weak fault detection, sensitization, and propagation tables

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2131 Quietest Results n If vector tests 1 new leakage/weak fault, select it for I DDQ measurement n Example circuit:

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2132 Results – Logic & I DDQ Tests I DDQ measurement vectors in bold & italics Time in units Time I I X O1 0 Time I I X O

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2133 Quietest Results Ckt. 1 2 # of Tran- Sistors # of Leakage Faults % Selected Vectors 0.5 % 0.99 % Leakage Fault Coverage % % # of Weak Faults % Selected Vectors 0.35 % 0.21 % Weak Fault Coverage 85.3 % % Ckt. 1 2

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2134 Instrumentation Problems Need to measure 10 kHz n Off-chip I DDQ measurements degraded  Pulse width of CMOS IC transient current  Impedance loading of tester probe  Current leakages in tester  High noise of tester load board n Much slower rate of current measurement than voltage measurement

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2135 Sematech Study n IBM Graphics controller chip – CMOS ASIC, 166,000 standard cells 0.8  m static CMOS, 0.45  m Lines (L eff ), 40 to 50 MHz Clock, 3 metal layers, 2 clocks n Full boundary scan on chip n Tests:  Scan flush – 25 ns latch-to-latch delay test  99.7 % scan-based stuck-at faults (slow 400 ns rate)  52 % SAF coverage functional tests (manually created)  90 % transition delay fault coverage tests  96 % pseudo-stuck-at fault cov. I DDQ Tests

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2136 Sematech Results n Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis n Data for devices failing some, but not all, tests. pass fail pass pass fail pass fail fail pass fail pass fail Scan-based Stuck-at IDDQ (5  A limit) Functional Scan-based delay

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2137 Sematech Conclusions n Hard to find point differentiating good and bad devices for I DDQ & delay tests n High # passed functional test, failed all others High # passed all tests, failed I DDQ > 5  A n Large # passed stuck-at and functional tests  Failed delay & IDDQ tests n Large # failed stuck-at & delay tests  Passed I DDQ & functional tests n Delay test caught delays in chips at higher Temperature burn-in – chips passed at lower T.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2138 Limitations of I DDQ Testing n Sub-micron technologies have increased leakage currents  Transistor sub-threshold conduction  Harder to find I DDQ threshold separating good & bad chips n I DDQ tests work:  When average defect-induced current greater than average good IC current  Small variation in I DDQ over test sequence & between chips n Now less likely to obtain two conditions

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 2139 Summary n I DDQ tests improve reliability, find defects causing:  Delay, bridging, weak faults  Chips damaged by electro-static discharge n No natural breakpoint for current threshold  Get continuous distribution – bimodal would be better n Conclusion: now need stuck-fault, I DDQ, and delay fault testing combined n Still uncertain whether I DDQ tests will remain useful as chip feature sizes shrink further