Gheorghe M. Ştefan

Comparator 2014Digital Integrated Circuits - week seven2

Elementary comparator 2014Digital Integrated Circuits - week seven3

Log-depth comparator 2014Digital Integrated Circuits - week seven4

Complex (random) circuits An universal circuit: 2014Digital Integrated Circuits - week seven5 Size  O(2 n ) Depth  O(n)

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2014Digital Integrated Circuits - week seven7 S EMUX = 6 S 3U_circuit = 42

2014Digital Integrated Circuits - week seven8 S 3InMajority = 12

Many-input random circuit 2014Digital Integrated Circuits - week seven9

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Applying the de Morgan theorem results a Read-Only Memory (ROM) which is not a memory, it is a combinational circuit implemented as a Look-Up Table (LUT). x n-1, x n-2, … x 0 : is the “address” f, g, … s : is the “content stored at” x n-1, x n-2, … x Digital Integrated Circuits - week seven12

First-order – 1-loop digital systems Elementary latch Clocked latch Master-slave flip flop: serial extension Random Access Memory (RAM): parallel extension Register: serial-parallel extension 2014Digital Integrated Circuits - week seven13

Stable – unstable loops 2014Digital Integrated Circuits - week seven14

Low-cost oscillator 2014Digital Integrated Circuits - week seven15

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Serial composition: serial shift register 2014Digital Integrated Circuits - week seven17

Parallel composition: Random Access Memory (RAM) 2014Digital Integrated Circuits - week seven18

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Expanding the number of bits 2014Digital Integrated Circuits - week seven20

Expanding the number of words 2014Digital Integrated Circuits - week seven21

Synchronous RAM 2014Digital Integrated Circuits - week seven22

For L < 130 nm writing is synchronous, while reading could be synchronous or asynchronous 2014Digital Integrated Circuits - week seven23 Example of synchronous reading:

Register file 2014Digital Integrated Circuits - week seven24

2014Digital Integrated Circuits - week seven25 Reading is asynchronous

Home work 7 Problem 1: Let be the log-depth comparator (see slide 4) with n = 8. Compute de size of the circuit (the number of inputs in all inverting circuits). Problem 2: Design, using the method presented in the slide no. 7, the circuit whose “program” is Compute the final size (the number of inputs in all inverting circuits). Problem 3: Let be the low cost oscillator form the slide 16. Its output is connected to the input of an inverter. 1. Compute the frequency of the signal generated, f osc, when: For the NAND gate: t pLH = 40ps, t pHL = 60ps For the first NOT (connected to the NAND’s output): t pLH = 50ps, t pHL = 30ps For the second NOT: t pLH = 100ps, t pHL = 60ps 2. What will be f osc if the output of the same oscillator will be connected to the input of two invertors instead of one? 2014Digital Integrated Circuits - week seven26