ECE Synthesis & Verification 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits Introduction to Logic Synthesis

ECE Synthesis & Verification 2 Synthesis Flow Logic synthesis HDL specification Techn-independent optimization Techn-independent optimization Technology mapping Technology mapping Cell library Manufacturing Front-end parsing Front-end parsing

module example(clk, a, b, c, d, f, g, h) input clk, a, b, c, d, e, f; output g, h; reg g, h; clk) begin g = a | b; if (d) begin if (c) h = a&~h; else h = b; if (f) g = c; else a^b; end else if (c) h = 1; else h ^b; end endmodule Specification d a b e f c 0 h g clk Logic Extraction Synthesis Flow a multi-stage process Technology-Independent Optimization f g0 h1 a c e g1 h3 h5 H G b d Technology-Dependent Mapping f d b e a c clk h H G g

Data Flow Graph (DFG) f a c e b d

ECE Synthesis & Verification 5 Typical Synthesis Scenario - read HDL - control/data flow analysis - basic logic restructuring - crude measures for goals - use logic gates from target cell library - timing optimization - physically driven optimizations RTL to Network Transformation Technology independent Optimizations Technology Mapping Technology Dependent Optimizations Test Preparation - improve testability - test logic insertion

ECE Synthesis & Verification 6 Local versus Global Transformations Local transformations optimize the function of one node of the network – –smaller area – –better performance – –map to a particular set of cells (library) Global transformations restructure the entire network – –merging nodes – –spitting nodes – –removing/changing connections between nodes Node representation: – –SOP, POS – –BDD – –Factored forms – –keep size bounded to avoid blow-up of local transformations

ECE Synthesis & Verification 7 Logic Optimization methods Logic Optimization Multi-level logic (standard cells) Multi-level logic (standard cells) Two-level logic (PLA) Exact (QM) Heuristic (espresso) Heuristic (espresso) Structural (SIS) Structural (SIS) Functional (AC, Kurtis) Functional (AC, Kurtis) Functional (BDD-based) Functional (BDD-based) algebraic Boolean

ECE Synthesis & Verification 8 General Logic Structure Combinational optimization –keep latches/registers at current positions, keep their function –optimize combinational logic in between Sequential optimization –change latch position/function (retiming) Combinational logic (CL) Sequential elements

ECE Synthesis & Verification 9 What is Logic Synthesis? D XY Given:Finite-State Machine F(X,Y,Z,, ) where: X: Input alphabet Y: Output alphabet Z: Set of internal states : X x Z Z (next state function, Boolean) : X x Z Y (output function, Boolean) Target:Circuit C(G, W) where: G: set of circuit components {Boolean gates, flip-flops, etc} W: set of wires connecting G Combinational logic Sequential logic

ECE Synthesis & Verification 10 Basic Model of Sequential circuit: FSM X=(x 1,x 2,…,x n ) Y=(y 1,y 2,…,y n )  S=(s 1,s 2,…,s n ) S’=(s’ 1,s’ 2,…,s’ n ) D M(X,Y,S,S 0, , ): X: Inputs Y: Outputs S: Current State S 0 : Initial State(s)  : X  S  S (next state function)  : X  S  Y (output function) Delay elements: Clocked: synchronous single-phase clock, multiple-phase clocks Unclocked: asynchronous Sequential synthesis: find (multi-level) implementation of  (X) and (X) that minimize its cost (area, delay, power)

ECE Synthesis & Verification 11 Optimization Criteria for Synthesis Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) Critical path delay of the longest path through the logic Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g. single or multiple stuck- at faults) Power consumed by the logic gates Noise Immunity Place-ability, Wire-ability The optimization criteria for logic optimization is to minimize some function of: while simultaneously satisfying misc. constraints

ECE Synthesis & Verification 12 Two-Level (PLA) vs. Multi-Level PLA control logic constrained layout highly automatic technology independent multi-valued logic input, output, state encoding Very predictable Multi-level Logic all logic general (standard cells, macro cells, blocks) automatic partially technology independent part of multi-level logic Very hard to predict E.g. Standard Cell Layout

ECE Synthesis & Verification 13 Two-level Logic: the PLA x 0 x 1 x 2 AND plane x 0 x 1 x 2 Product terms OR plane f 0 f 1

ECE Synthesis & Verification 14 Two-Level Logic Minimization Inverting format (NOR- NOR) more effective Every logic function can be expressed in sum-of-products format (AND-OR) minterm

ECE Synthesis & Verification 15 Programmable Logic Array GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND-planeOR-plane Pseudo-NMOS PLA

ECE Synthesis & Verification 16 Transformation-based Synthesis All modern synthesis systems are build that way – –Series of transformations that change network representation work on uniform network representation – –“script” of “scenario” that can combine those transformations to a overall greedy Transformations differ in: – –their scope local versus global restructuring – –the domain they optimize combinational versus sequential timing versus area technology independent versus technology dependent – – the underlying algorithms they use BDD based, SAT based, structure based, etc.

ECE Synthesis & Verification 17 Network Representation Boolean network: directed acyclic graph (DAG) node logic function representation f j (x,y) node variable y j : y j = f j (x,y) edge (i,j) if f j depends explicitly on y i Inputs x = (x 1, x 2,…,x n ) Outputs z = (z 1, z 2,…,z p ) External don’t cares: d 1 (x), …, d p (x)

ECE Synthesis & Verification 18 Sum of Products (SOP) Example: abc’+a’bd+b’d’+b’e’f (sum of cubes) Advantages: easy to manipulate and minimize many algorithms available (e.g. AND, OR, TAUTOLOGY) two-level theory applies Disadvantages: Not representative of logic complexity. For example: f = ad+ae+bd+be+cd+ce f’ = a’b’c’+d’e’ These differ in their implementation by an inverter. Not easy to estimate logic size and performance Difficult to estimate progress during logic manipulation

ECE Synthesis & Verification 19 Factored Forms Example: (ad+b’c)(c+d’(e+ac’))+(d+e)fg Advantages good representative of logic complexity f=ad+ae+bd+be+cd+ce f’=a’b’c’+d’e’  f=(a+b+c)(d+e) in many designs (e.g. complex gate CMOS) the implementation of a function corresponds directly to its factored form good estimator of logic implementation complexity doesn’t blow up easily Disadvantages not as many algorithms available for manipulation hence often just convert into SOP before manipulation

ECE Synthesis & Verification 20 Binary Decision Diagrams (BDDs) Like factored form, represents both function and complement Like network of muxes, but restricted since controlled by primary input variables not really a good estimator for implementation complexity Given an ordering, reduced BDD is canonical, hence a good replacement for truth tables For a good ordering, BDDs remain reasonably small for complicated functions (e.g. not multipliers) Manipulations are well defined and efficient True support (dependency) is displayed

ECE Synthesis & Verification 21 AND-INVERTER Graphs (AIG) Base data structure uses two-input AND function for vertices and INVERTER attributes at the edges (individual bit) – –use De’Morgan’s law to convert OR operation etc. Hash table to identify and reuse structurally isomorphic circuits f g g f Means complement