RISC vs CISC CS 3339 Lecture 3.2 Apan Qasem Texas State University Spring 2015 Some slides adopted from Milo Martin at UPenn

Review : CPU Performance Main performance equation CPU Time = Instruction Count * CPI * Clock Cycle Time CPU Time = (instructions/program) * (cycles/instruction) * (seconds/cycle) Architects want to reduce CPU Time This can be done by Decreasing instruction count Decreasing CPI Decreasing Clock cycle time Combination of any of the above

Review : CPU Performance Main performance equation CPU Time = IC * CPI * CC CPU Time = (instructions/program) * (cycles/instruction) * (seconds/cycle) Say, you develop a new generation of processors that is twice as fast as the previous generation. How will this affect the performance equation? MetricIncreaseDecreaseWon’t affect/Don’t know IC CPI CC ✔ ✔ ✔

Review : CPU Performance Main performance equation CPU Time = IC * CPI * CC CPU Time = (instructions/program) * (cycles/instruction) * (seconds/cycle) Say, you add a new instruction to the ISA that allows you to do a load and store operation using the same instruction. Assuming all programs perform some number of loads and stores, how will this affect the performance equation? MetricIncreaseDecreaseWon’t affect/Don’t know IC CPI CC ✔ ✔ ✔

Review : CPU Performance Main performance equation CPU Time = IC * CPI * CC CPU Time = (instructions/program) * (cycles/instruction) * (seconds/cycle) Say, you remove indirect addressing mode from your ISA and so the only addressing mode supported is immediate addressing. How will this change, affect the performance equation? MetricIncreaseDecreaseWon’t affect/Don’t know IC CPI CC ✔ ✔ ✔

RISC vs. CISC Performance Argument Main performance equation CPU Time = Instruction Count * CPI * Clock Cycle Time CISC (Complex Instruction Set Computing) Reduce instruction count with “complex” instructions If each instruction does more then need fewer instructions Tends to increase CPI or clock cycle time RISC (Reduced Instruction Set Computing) Improve CPI with many single-cycle instructions Increases instruction count, but hopefully not as much Help from smart compiler (Perhaps) improve clock cycle time via aggressive implementation allowed by simpler instructions

History RISC: reduced-instruction set computing Coined by Patterson in early 80’s RISC machines existed before the 80s but they were not called RISC First designs Berkeley RISC-I (Patterson) Stanford MIPS (Hennessy) IBM 801 (Cocke) Examples: ARM, PowerPC, SPARC, Alpha, PA-RISC CISC: complex-instruction set computing Term didn‘t exist before RISC Examples: x86, VAX, Motorola Philosophical War

History Pre 1975 Bad compilers (so assembly written by hand) Complex, high-level ISAs (easier to write assembly) 1975-… Moore’s Law makes fast single-chip microprocessor possible… …but only for small, simple ISAs Performance advantage of this integration was compelling Compilers had to get involved in a big way RISC manifesto: create ISAs that… Simplify single-chip implementation Facilitate optimizing compilation

Key Differences Single-cycle execution Load/store architecture Few memory addressing modes Fixed-length instruction format Reliance on compiler optimizations Many registers (compilers are better at using them) Many multi-cycle operations Register-memory and memory- memory Many modes Many formats and lengths Hand assemble to get good performance Few registers RISCCISC

Current Winner (Revenue): CISC x86 (Intel) Intel sells the most non-embedded processors Has taken over the high-end market in recent years x86 was first 16-bit microprocessor by ~2 years IBM put it into its PCs because there was no competing choice Moore’s law has helped Intel in a big way Most engineering problems can be solved with more transistors

Current Winner (Volume): RISC ARM

ARM ISA ARM (Acorn RISC Machine ! Advanced RISC Machine) First ARM chip in mid-1980s (from Acorn Computer Ltd). 1.2 billion units sold in 2004 (>50% of all 32/64-bit CPUs) Low-power and embedded devices 32-bit RISC ISA 16 registers, PC is one of them Many addressing modes, e.g., auto increment Condition codes, each instruction can be conditional Multiple implementations X-scale (design was DEC’s, bought by Intel, sold to Marvell) Others: Freescale (was Motorola), Texas Instruments, STMicroelectronics, Samsung, Sharp, Philips, etc.

Intel’s Compatibility Trick: RISC Inside 1993: Intel wanted out-of-order execution in Pentium Pro Hard to do with a coarse grain ISA like x86 Solution? Translate x86 to RISC μops in hardware Processor maintains x86 ISA externally for compatibility But executes RISC μISA internally for implementability Idea co-opted by other x86 companies AMD and Transmeta Not part of the ISA specification, semi-public information