 M.A - BIS Workshop – 4th of February 2015 BIS software layers at CERN Maxime Audrain BIS workshop for CERN and ESS, 3-4 of February 2015 On behalf of.

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Presentation transcript:

 M.A - BIS Workshop – 4th of February 2015 BIS software layers at CERN Maxime Audrain BIS workshop for CERN and ESS, 3-4 of February 2015 On behalf of the TE-MPE-MS Software Team: C. Aguilera, S. Boychenko, M. Dragu, R. Heil, J.-C. Garnier, M. Koza, K.H. Krol, K.Stamos

2 Content BIS software vertical slice overviewDiagnostic and safety servicesSoftware qualityAdaptable architecture

3 Architecture overview M.A - BIS Workshop – 4th of February 2015

4 BIS software vertical slice overviewDiagnostic and safety servicesSoftware qualityAdaptable architecture

5 BIS Hardware  VME crate containing a (Linux based) controller and multiple VME boards.  Communication is based on the VME bus.  Controller can talk to the outside world through Ethernet (machine/technical network).  More details in Stephane presentation. M.A - BIS Workshop – 4th of February 2015

6 CERN VME Driver  Runs on the Linux controller of the VME crate.  Interface between VME boards and FESA classes.  Access to hardware devices occurs through two mechanisms:  I/O operations over registers  Interrupts  Driver generated from hardware types information stored in the Controls Configuration DB (CCDB). M.A - BIS Workshop – 4th of February 2015

7 FESA  FESA = Front End Software Architecture, framework developed at CERN to standardize device access throughout accelerator equipment.  C++ program running on the Linux controller of the VME crate.  Interface between the board drivers and the ‘high-level’ software layers.  Defines a contract (Device Property model) that exposes fields to be acquired or controlled.  Allows read/write and subscribe operations. Real-time processing of the boards data is synchronized using the accelerators timing system or FESA internal timer.  For the BIS, no specific logic, only expose the registers with un-decoded raw data. M.A - BIS Workshop – 4th of February 2015

8 CMW  Controls MiddleWare (CMW) is the communication infrastructure at CERN based on CORBA/ZeroMQ. Bridge between Java and C++ worlds. M.A - BIS Workshop – 4th of February 2015

9 BIS GUI (1/2)  Main application for monitoring and control of all BICs at CERN.  Operator/experts panels and commands.  Timing synchronous monitoring for the cyclic machines (SPS, Booster, Linac4). M.A - BIS Workshop – 4th of February 2015

10 BIS GUI (2/2) M.A - BIS Workshop – 4th of February 2015

11 BIS software vertical slice overviewDiagnostic and safety servicesSoftware qualityAdaptable architecture

12 Controls configuration database  Stores static BIS reference configuration (BIS input names, connection type to user, etc…).  Used mainly by the pre-operational checks to verify consistency with the hardware. M.A - BIS Workshop – 4th of February 2015

13 Diagnostic services  Record of all BIS boards history buffers in the Logging DB to be accessible later on to replay operational states and analyse certain events. Acquisition every second.  Record BIS history buffer and other information on configurable events in the Post-Mortem System: e.g. beam dump, etc. Used then in the post-operational checks. M.A - BIS Workshop – 4th of February 2015

14 Operational checks  Pre-operational :  using the LHC sequencer to run a Java program to verify certain configuration or current states of the BIS before operation.  Operation/next cycle can be inhibited.  Post-operational:  with Post Mortem to analyse the BIS buffers around a beam dump and determine potential problems related to the system.  Operation/next cycle can be inhibited. M.A - BIS Workshop – 4th of February 2015

15 Continuous Monitoring  DiaMon framework to monitor the FEC state.  During-operation: using the DiaMon framework, to assert certain values of the BIS boards register and trigger different severity messages. M.A - BIS Workshop – 4th of February 2015

16 Software Interlock System  Can interlock each BIC in the LHC through a dedicated software input.  Can inhibit operation if additional interlocking constraints are not met (typically for more complex/less critical/redundant verifications like power-converters statuses, LHC access, etc…).  Timeout to inhibit operation if the SIS connection to the BIS is lost. M.A - BIS Workshop – 4th of February 2015

17 BIS software vertical slice overviewDiagnostic and safety servicesSoftware qualityAdaptable architecture

18 Scrum  Individuals and interactions over Processes and tools  Working software over Comprehensive documentation  Customer collaboration over Contract negotiation  Responding to change over Following a plan M.A - BIS Workshop – 4th of February 2015

19 Quality tools (1/2)  Sonarqube for quality metrics,  Distribution of quality profiles to developer machines  Eclipse workstation configuration with Eclipse SDC:  Static code checkers configuration,  Code coverage plug-ins,  Code generation plug-ins. M.A - BIS Workshop – 4th of February 2015

20 Quality tools (2/2) M.A - BIS Workshop – 4th of February 2015

21 Continuous delivery  Using Bamboo and Gradle to ensure all-time delivery capability.  Product tested and released each time new code is added.  Release candidate build runs the acceptance tests to ensure the product is deployable.  Deployment plan -> “Click to deploy” M.A - BIS Workshop – 4th of February 2015

22 BIS software vertical slice overviewDiagnostic and safety servicesSoftware qualityAdaptable architecture

23 Adaptable architecture (1/4) M.A - BIS Workshop – 4th of February 2015  VME driver  CERN version -> EPICS version  FESA  EPICS module or Real-Time Java or other C++ implementation  Genericity from board type.  CMW -> EPICS MiddleWare

24 Adaptable architecture (2/4)  BIS GUI will need some adaptation to select a communication API according to the context: ESS, CERN  Role Based Access -> EPICS Security module?  CCDB  any data source: DB, CSV, etc..  Logging Service  Any continuous acquisition service backed by a “write once read many” storage: e.g. Cassandra, etc… M.A - BIS Workshop – 4th of February 2015

25 Adaptable architecture (3/4)  Pre-Op  Use EPICS sequencer?  Need communication adaptation (EPICS MW)  Re-use or complement logic  Post-op  Could use PM data collection (PM tightly coupled to CMW)  Analysis framework required -> eDSL M.A - BIS Workshop – 4th of February 2015

26 Adaptable architecture (4/4)  Continuous monitoring  DiaMon can be replaced by any free and open source solution: Nagios, Icinga, Shinken.  Software Interlock System  CERN core with ESS specific modules?  Can be re-implemented. M.A - BIS Workshop – 4th of February 2015

27 New architecture overview M.A - BIS Workshop – 4th of February 2015

28 Outlook  Complete CERN infrastructure for BIS supervision and diagnostic  Partly reusable and/or adaptable  Interested for collaboration! M.A - BIS Workshop – 4th of February 2015

29 Thank you for your attention  Do you have any questions? M.A - BIS Workshop – 4th of February 2015