Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL Code for a Binary Divider 20.4VHDL Code for a Dice Game Simulator 20.5Concluding Remarks

Nonlinear & Neural Networks LAB. Objectives 1. Given a block diagram and state graph for a digital system’s control unit. Write behavioral VHDL code for system. Use one clocked process 2. Compile and simulate VHDL code you wrote for step 1 3. Write synthesizable VHDL code for the system using control signals. Use two processes, one for combinational logic and one for updating registers 4. Compile, simulate, and synthesize the VHDL code for step.3 5. Write a VHDL test bench to test a VHDL module

Nonlinear & Neural Networks LAB VHDL Code for a Serial Adder Fig VHDL Code for Figure 18-1

Nonlinear & Neural Networks LAB. Fig (Continued) 20.1 VHDL Code for a Serial Adder

Nonlinear & Neural Networks LAB VHDL Code for a Binary Multiplier Fig Behavioral VHDL Code for Multiplier of Figure 18-7

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) ‘ 0 ’ &ACC(7 downto 4) + Mcand 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Command File and Simulation Results for (13 by 11) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Test Bench for Multiplier [loop-label:] for index in range loop sequential statements end loop [loop-label]; 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Test Bench for Multiplier 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Command File and Simulation of Multiplier 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Two-Process VHDL Model for Multiplier 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Block Diagram for 8X8 Binary Multiplier 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig VHDL Code for Multiplier with Shift Counter 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig (Continued) 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB. Fig Command File and Simulation of 8X8 Multiplier 20.2 VHDL Code for a Binary Multiplier

Nonlinear & Neural Networks LAB VHDL Code for a Binary Divider Fig VHDL Code for Divider

Nonlinear & Neural Networks LAB. Fig (Continued) 20.3 VHDL Code for a Binary Divider

Nonlinear & Neural Networks LAB. Fig (Continued) 20.3 VHDL Code for a Binary Divider

Nonlinear & Neural Networks LAB VHDL Code for a Dice Game Simulator Fig VHDL Code for Dice Game Controller

Nonlinear & Neural Networks LAB. Fig (Continued) 20.4 VHDL Code for a Dice Game Simulator

Nonlinear & Neural Networks LAB. Fig Counter Module for Dice Game 20.4 VHDL Code for a Dice Game Simulator

Nonlinear & Neural Networks LAB. Fig Main Module for Dice Game 20.4 VHDL Code for a Dice Game Simulator

Nonlinear & Neural Networks LAB Concluding Remarks TABLE 20-1 Synthesis Results (Optimized for Area)