Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Spring 2011ECE Digital Systems Design2 The Design Process Design conception VHDL Schematic capture DESIGN ENTRY Design correct? Functional simulation No Yes No Synthesis Physical design Chip configuration Timing Requirements met? Timing simulation Yes

Spring 2011ECE Digital Systems Design3 Introduction to VHDL What is VHDL?  Very High Speed Integrated Circuit (VHSIC)  Hardware  Description  Language VHDL is a formal language for specifying the behavior and structure of a digital circuit. Verilog is another, equally popular, hardware description language (HDL).

Spring 2011ECE Digital Systems Design4 Hardware Description Languages Both VHDL and Verilog are hardware description languages. They describe hardware! They are not software programming languages. This is an important, but difficult, concept to understand.

Spring 2011ECE Digital Systems Design5 VHDL Designs A VHDL design is composed of two parts:  Entity  Architecture The entity statement defines the interface to the circuit (i.e. inputs and outputs). The architecture statement describes the implementation of the circuit.

Spring 2011ECE Digital Systems Design6 The Entity Statement Defines the input and output of the design. entity entity-name is port( port-name-A: mode type; port-name-B: mode type; port-name-C: mode type; … ); end [entity][entity-name];

Spring 2011ECE Digital Systems Design7 Ports Each I/O signal in the entity statement is referred to as a port. A port is analogous to a pin on a schematic. Similar to variables in a HLL, a port is a data object.  Can be assigned values.  Can be used in expressions.

Spring 2011ECE Digital Systems Design8 Mode The mode describes the direction in which data is transferred through a port. There are 4 different modes: ModeDescription inData only flows into the entity (input) outData only flows out of the entity (output) inoutData flows into or out of the entity (bidirectional) bufferUsed for internal feedback

Spring 2011ECE Digital Systems Design9 Type VHDL is a strongly typed language.  Data objects of different types cannot be assigned to one another without the use of a type-conversion function. There are two broad categories of data types:  scalar stores a single value  composite stores multiple values

Spring 2011ECE Digital Systems Design10 Types The VHDL data types include: bit boolean integer character std_ulogic std_logic bit_vector string std_ulogic_vector std_logic_vector scalar composite

Spring 2011ECE Digital Systems Design11 Types The most useful types for synthesis and simulation, provided by the IEEE std_logic_1164 package, are:  std_logic  std_ulogic  std_logic_vector  std_ulogic_vector

Spring 2011ECE Digital Systems Design12 IEEE Standard Logic Types Use of two-valued logic (bit and bit_vector) is generally not sufficient to simulate digital systems. In addition to 0 and 1, Z (high-impedance), X (unknown), and U (uninitialized) are often used in digital system simulation. The IEEE standard 1164 defines the std_logic type that has nine values:  0, 1, Z, X, U, W, L, H, - Use std_logic and std_logic_vector in your designs.

Spring 2011ECE Digital Systems Design13 The Architecture Statement Describes the implementation of the design.  Specifies the function of the design. architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture][architecture-name];

Spring 2011ECE Digital Systems Design14 The Architecture Statement One or more architecture statements may be associated with an entity statement.  Only one may be referenced at a time. Declarations  Signals and components. Architecture body  Statements that describe the functionality of the design (i.e. the circuit).

Spring 2011ECE Digital Systems Design15 Architecture Body Several different models, or styles, may be used in the architecture body, including:  Behavioral Dataflow Algorithmic  Structural These models allow you to describe the design at different levels of abstraction.  Algorithms → Gates

Spring 2011ECE Digital Systems Design16 Behavioral Model Specify a set of statements to model the function, or behavior, of the design. Dataflow: uses concurrent statements Algorithmic: uses sequential statements

Spring 2011ECE Digital Systems Design17 Structural Model Specify a set of statements to instantiate and interconnect the components necessary for the design. Components are defined separately. Signals are used to interconnect components. Results in a hierarchical design.

Spring 2011ECE Digital Systems Design18 Components A component is a predefined element used in an hierarchical design. Component declaration component component-name port(port-name-A: mode type; port-name-B: mode type; … ); end component;

Spring 2011ECE Digital Systems Design19 Components Component instantiation label: component-name port map(port-name-A => signal-name-A, port-name-B => signal-name-B, … ); The above mapping of port names to signal names is known as named association.  Positional association may also be used.

Spring 2011ECE Digital Systems Design20 Signals A signal is used to interconnect components in an hierarchical design. Signal declaration signal signal-name: type;

Spring 2011ECE Digital Systems Design21 Statements Concurrent statements  All are executed at the same time.  The order is unimportant. Sequential statements  Executed in the order in which they are listed.  The order is very important. The Process statement  Sequential statements must be enclosed within a process statement.

Spring 2011ECE Digital Systems Design22 Statements signal assignment conditional signal assignment selected signal assignment signal assignment if-then-else case for loop Concurrent Sequential

Spring 2011ECE Digital Systems Design23 The Process Statement The process statement is used to define an algorithm. The process, or algorithm, is composed of a set of sequential statements.  The sequential statements and their order define the algorithm. All process statements execute concurrently. A process statement has a sensitivity list.

Spring 2011ECE Digital Systems Design24 Operators Logical and, or, nand, nor, xor, xnor Relational =, /=,, >= Shift sll, srl, sla, sra, rol, ror Addition / Subtraction +, -, & (concatenate) Multiplication / Division *, /, mod, rem Unary +, - Miscellaneous not, abs, ** (exponent) Assignment<=

Spring 2011ECE Digital Systems Design25 Synthesis A design can be synthesized using any of the architecture models. However, one model may be more optimal than another, depending on the criteria and constraints of the design. Regardless of the model used, a netlist is generated in the synthesis process. The netlist is then “programmed” into a PLD to realize the design.

Spring 2011ECE Digital Systems Design26 Basic Conventions VHDL is case insensitive. It is a free-format language.  Allows spacing for readability All statements must end with a semicolon. Comments start with “--” and continue to the end of the line.

Spring 2011ECE Digital Systems Design27 Basic Conventions All names and labels should start with a letter. They should contain only alphanumeric characters and the underscore.  Should not have 2 consecutive underscores.  Should not end with an underscore. All names and labels should be unique  within a given entity and architecture.

Spring 2011ECE Digital Systems Design28 Basic Conventions Filename should match entity name. Only one entity per file. There may be more than one architecture for each entity.  However, only one architecture may be associated with an entity at any point in time.

Spring 2011ECE Digital Systems Design29 A simple logic circuit Example F A B C B C A B A C

Spring 2011ECE Digital Systems Design30 Signal Assignment signal-name <= expression [after delay]; Can be a signal or a port.

Spring 2011ECE Digital Systems Design31 Conditional Signal Assignment signal-name <= expression1 when condition1 elseexpression2 when condition2 elseexpression3 when condition3 … ; [after delay] can be included after each of the expressions

Spring 2011ECE Digital Systems Design32 Selected Signal Assignment with expression select signal-name <= expression1 when choice1, expression2 when choice2,... expressionN when others; [after delay] can be included after each of the expressions

Spring 2011ECE Digital Systems Design33 Example: A simple logic circuit F A B C B C A B A C Entity Architecture

Spring 2011ECE Digital Systems Design34 Example: Entity

Spring 2011ECE Digital Systems Design35 Example: Architecture #1 Behavioral Model

Spring 2011ECE Digital Systems Design36 Example: Architecture #2 Behavioral Model

Spring 2011ECE Digital Systems Design37 Example: Architecture #3

Spring 2011ECE Digital Systems Design38 Example: Architecture #3 (cont.) Structural Model

Spring 2011ECE Digital Systems Design39 Arithmetic Operations on Standard Logic Vectors The basic IEEE standards do not define arithmetic operations for bit_vectors or std_logic_vectors. The package IEEE.Std_logic_unsigned defines arithmetic operations on std_logic_vectors. The arithmetic operators (+, −, and *) and comparison operators ( =, >) defined in this package treat std_logic_vectors as unsigned binary numbers. These operators are referred to as overloaded operations. This means that the compiler will automatically use the proper definition of the operator depending on its context.

Spring 2011ECE Digital Systems Design40 Questions?