Nick McKeown CS244 Lecture 6 Packet Switches. What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never.

Slides:



Advertisements
Similar presentations
EE384y: Packet Switch Architectures
Advertisements

1 Maintaining Packet Order in Two-Stage Switches Isaac Keslassy, Nick McKeown Stanford University.
1 Outline  Why Maximal and not Maximum  Definition and properties of Maximal Match  Parallel Iterative Matching (PIM)  iSLIP  Wavefront Arbiter (WFA)
1 Statistical Analysis of Packet Buffer Architectures Gireesh Shrimali, Isaac Keslassy, Nick McKeown
Router Architecture : Building high-performance routers Ian Pratt
Submitters: Erez Rokah Erez Goldshide Supervisor: Yossi Kanizo.
Worst-case Fair Weighted Fair Queueing (WF²Q) by Jon C.R. Bennett & Hui Zhang Presented by Vitali Greenberg.
Algorithm Orals Algorithm Qualifying Examination Orals Achieving 100% Throughput in IQ/CIOQ Switches using Maximum Size and Maximal Matching Algorithms.
Making Parallel Packet Switches Practical Sundar Iyer, Nick McKeown Departments of Electrical Engineering & Computer Science,
Providing Performance Guarantees in Multipass Network Processors Isaac KeslassyKirill KoganGabriel ScalosubMichael Segal EE, TechnionCISCO & CSE, BGU.
April 10, HOL Blocking analysis based on: Broadband Integrated Networks by Mischa Schwartz.
1 Comnet 2006 Communication Networks Recitation 5 Input Queuing Scheduling & Combined Switches.
CS 552 Computer Networks IP forwarding Fall 2004 Rich Martin (Slides from D. Culler and N. McKeown)
1 Architectural Results in the Optical Router Project Da Chuang, Isaac Keslassy, Nick McKeown High Performance Networking Group
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Input-Queued.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion MSM.
CSIT560 by M. Hamdi 1 Course Exam: Review April 18/19 (in-Class)
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion The.
1 Internet Routers Stochastics Network Seminar February 22 nd 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
EE 122: Router Design Kevin Lai September 25, 2002.
CS 268: Lecture 12 (Router Design) Ion Stoica March 18, 2002.
1 EE384Y: Packet Switch Architectures Part II Load-balanced Switches Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
1 Trend in the design and analysis of Internet Routers University of Pennsylvania March 17 th 2003 Nick McKeown Professor of Electrical Engineering and.
COMP680E by M. Hamdi 1 Course Exam: Review April 17 (in-Class)
1 Achieving 100% throughput Where we are in the course… 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic,
Core Stateless Fair Queueing Stoica, Shanker and Zhang - SIGCOMM 98 Rigorous fair Queueing requires per flow state: too costly in high speed core routers.
1 Netcomm 2005 Communication Networks Recitation 5.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Maximal.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scheduling.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York Stony Brook.
1 IP routers with memory that runs slower than the line rate Nick McKeown Assistant Professor of Electrical Engineering and Computer Science, Stanford.
Computer Networks Switching Professor Hui Zhang
Load Balanced Birkhoff-von Neumann Switches
Nick McKeown CS244 Lecture 7 Valiant Load Balancing.
Dynamic Networks CS 213, LECTURE 15 L.N. Bhuyan CS258 S99.
CS 552 Computer Networks IP forwarding Fall 2005 Rich Martin (Slides from D. Culler and N. McKeown)
Enabling Class of Service for CIOQ Switches with Maximal Weighted Algorithms Thursday, October 08, 2015 Feng Wang Siu Hong Yuen.
Summary of switching theory Balaji Prabhakar Stanford University.
1 IK1500 Communication Systems IK1500 Anders Västberg
The Router SC 504 Project Gardar Hauksson Allen Liu.
Routers. These high-end, carrier-grade 7600 models process up to 30 million packets per second (pps).
ISLIP Switch Scheduler Ali Mohammad Zareh Bidoki April 2002.
Packet Forwarding. A router has several input/output lines. From an input line, it receives a packet. It will check the header of the packet to determine.
1 Performance Guarantees for Internet Routers ISL Affiliates Meeting April 4 th 2002 Nick McKeown Professor of Electrical Engineering and Computer Science,
Crossbar Switch Project
Stress Resistant Scheduling Algorithms for CIOQ Switches Prashanth Pappu Applied Research Laboratory Washington University in St Louis “Stress Resistant.
Nick McKeown Spring 2012 Lecture 2,3 Output Queueing EE384x Packet Switch Architectures.
Winter 2006EE384x1 EE384x: Packet Switch Architectures I a) Delay Guarantees with Parallel Shared Memory b) Summary of Deterministic Analysis Nick McKeown.
T. S. Eugene Ngeugeneng at cs.rice.edu Rice University1 COMP/ELEC 429 Introduction to Computer Networks Lecture 18: Quality of Service Slides used with.
Buffered Crossbars With Performance Guarantees Shang-Tse (Da) Chuang Cisco Systems EE384Y Thursday, April 27, 2006.
SNRC Meeting June 7 th, Crossbar Switch Scheduling Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University
Intel Slide 1 A Comparative Study of Arbitration Algorithms for the Alpha Pipelined Router Shubu Mukherjee*, Federico Silla !, Peter Bannon $, Joel.
1 A quick tutorial on IP Router design Optics and Routing Seminar October 10 th, 2000 Nick McKeown
Improving Matching algorithms for IQ switches Abhishek Das John J Kim.
Input buffered switches (1)
Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai.
1 Building big router from lots of little routers Nick McKeown Assistant Professor of Electrical Engineering and Computer Science, Stanford University.
scheduling for local-area networks”
Weren’t routers supposed
CS 268: Router Design Ion Stoica February 27, 2003.
Packet Forwarding.
Addressing: Router Design
Packet Scheduling/Arbitration in Virtual Output Queues and Others
Outline Why Maximal and not Maximum
EE 122: Lecture 7 Ion Stoica September 18, 2001.
COMP/ELEC 429 Introduction to Computer Networks
Techniques and problems for
Introduction to Packet Scheduling
Introduction to Packet Scheduling
Presentation transcript:

Nick McKeown CS244 Lecture 6 Packet Switches

What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never even considered the role of switching technology in overall network throughput. I had assumed that link throughput was the key determinant, so reading this paper made me realize how high-level improvements in network performance can be contingent upon advancements in several different areas of the networking stack. 2

Output Queued Packet Switch Lookup Address Update Header Forwarding Table Forwarding Table Lookup Address Update Header Forwarding Table Forwarding Table Lookup Address Update Header Forwarding Table Forwarding Table Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory Queue Packet Buffer Memory Buffer Memory DataH H H

Lookup Address Update Header Forwarding Table Forwarding Table Queue Packet Buffer Memory Buffer Memory Lookup Address Update Header Forwarding Table Forwarding Table Queue Packet Buffer Memory Buffer Memory Lookup Address Update Header Forwarding Table Forwarding Table Queue Packet Buffer Memory Buffer Memory Input Queued Packet Switch DataH H H

Head of Line Blocking

Virtual Output Queues

7 Output Queued Packet Switch The best that any queueing system can achieve.

Properties of OQ switches 1.They are “work conserving”. 2.Throughput is maximized. 3.Expected delay is minimized. 4.We can control packet delay. Broadly speaking: When possible, use an OQ design. 8

9 Input Queued Packet Switch Head of Line Blocking OQ Switch

Input Queued Packet Switch With Virtual Output Queues OQ Switch VOQs

What you said "... It seems like the paper assumes that, outside of overflowing buffers, no packets will ever be lost. I'd like to know where this assumption comes from. I feel like there are always random drops or packet corruption, so I have a hard time believing that these delay guarantees are 100% valid.” - Anonymous 11

Properties of OQ switches 1.They are “work conserving”. 2.Throughput is maximized. 3.Expected delay is minimized. 4.We can control packet delay. Broadly speaking: When possible, use an OQ design. 12

Practical Goal Problem: Memory bandwidth Therefore: Try to approximate OQ. In this paper, we are just looking at those switches that attempt to match “Property 2: Maximize throughput” 13

Questions 1. What is a virtual output queue (VOQ)? 2. How does a VOQ help? 3. What does the scheduler/arbiter do? 14

Parallel Iterative Matching Request Grant Accept uar selection #1 #2 Iteration :

PIM Properties 1. Guaranteed to find a maximal match in at most N iterations. 2. Inputs and outputs make decisions independently and in parallel. 3. In general, will converge to a maximal match in < N iterations. 4. How many iterations should we run?

Parallel Iterative Matching Simulation 16-port switch Uniform iid traffic FIFO Maximum Size Output Queued

Parallel Iterative Matching PIM with one iteration Simulation 16-port switch Uniform iid traffic FIFO Maximum Size Output Queued

Parallel Iterative Matching PIM with one iteration Simulation 16-port switch Uniform iid traffic PIM with four iterations

Parallel Iterative Matching Number of iterations Consider the n requests to output j Requesting inputs receiving no other grants Requesting inputs receiving other grants k n-k j

Virtual Output Queues 

Throughput “Maximize throughput” is equivalent to “queues don’t grow without bound for all non-oversubscribing traffic matrices” i.e.  for every queue in the system. Observations: 1.Burstiness of arrivals does not affect throughput 2.When traffic is uniform, solution is trivial 22

Uniform traffic 23 = 1/ N 1 1 … 1 … … … 1 1 … 1 

Throughput for uniform traffic 100% throughput is easy for uniform traffic: 1.Serve every queue at rate 1/N in fixed round- robin schedule 2.Pick a permutation each time uniformly and at random from all possible N! permutations 3.Or, from among N round-robin permutations 4.Wait until all VOQs are non-empty, then pick any algorithm above. 24

With non-uniform traffic 100% throughput is now known to be theoretically possible with: - Input queued switch, with VOQs, and - An arbiter to pick a permutation to maximize the total matching weight (e.g. weight is VOQ occupancy or packet waiting time) It is practically possible with: - IQ switch, VOQs, all running twice as fast - An arbiter running a maximal match (e.g. PIM) 25

Questions 1. Why does the PIM paper talk about TDM scheduled traffic? 2. What about multicast? 3. Multiple priorities? 26

Question What else does a router need to do apart from switching packets? 27