Evaluation of branch-prediction methods on traces from commercial applications R.B. Hilgendorf, G. J. Helm, W. Rosenstiel

Progress? Significant, but it is still not clear which, if any, of the currently advocated methods is superior. SPECmark test suite traces are often used –The gcc trace seems to be the most difficult for branch-prediction

Effect of Multitasking OS Increases the activity in a processor For the IBM ESA/390 series there exists a completely different set of traces that show the involvement of the OS

Trace Description T1: Transaction processing such as database queries in warehouse management T2: Interactive usage in program development. Searching, compiling. T3: Transaction processing from tasks such as hotel reservations. T4: Commercial batch jobs.

Distinction Static branches. Found in the binary program. Eliminate duplicates. Dynamic branches. Occur when running a program. Found in the trace. The term dynamic instructions means the total number of instructions in the trace.

The ESA/390 Instruction Set About 17 different branch instructions The majority of these in the traces receive their target address –From a general purpose register –A base register plus an index register plus a constant Coding the index register as zero will force even unconditional branches never to branch When using a certain mask all branches will take

Continued Using only the opcode of a branch will not provide enough information A further obstacle is that there is no distinct call and no return instruction

Branch Target Buffer Is intended to contain the target address for each branch and prediction information Normally addressed using the instruction address of the branch instruction Various techniques fold the complete address space into a usable BTB of affordable size

Continued If a branch is not in the BTB, that counts as a miss –First or cold misses plus misses due to replacement For small BTBs replacement misses dominate

Continued Large BTB –BTB stores effective addresses, not absolute addresses. –After a task switch part of the BTB content is useless, or worse, conterproductive –Instructions that are not even branches may be predicted

Continued Modern processors generally fetch more than a single instruction per cycle –An address range must be tested for a branch – put block addresses in the table Not preferable

Local History Pattern% TakenPrediction NNN7.8NT NNT34.1NT NTN51.9T NTT67.9T TNN32.6NT TNT64.4T TTN79.1T TTT97.7T

Global History One large history register Addresses a table of two-bit saturation counters –Incremented when a branch is taken, decremented when a branch is not taken, but 3++ = 3 and 0-- = 0 –Best! A path is used to predict!

Moving Targets We have assumed so far that –The target address in the BTB was correct –We only have to worry about taken/not taken Some branches may have different target addresses –Return –Indirect branches Case statement, jump tables, computed go-tos

Moving Targets (contd) If you have specific call and return instructions, you can use a return stack to get 100% prediction on returns. The ESA/390 does not have such instructions (neither does SPARC) A branch can be used as a call or a return

Continued An identification stack into which each possible call is written with its target and return address A return cache that receives new entries from the IS when the stored RA matches the target address of a possible return.