[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 05 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Old Version Wire routing on each block

Old Version.2

Current Version

16:1 MUX (11bits)

Data Input Routing

 We think the current layout of 16:1MUX (11bits) is not good enough.  Because of the Data Inputs Routing, it is very complex, now. (you can see the Data input routing picture)

 Maybe, we should refine the layout to this way. (16 inputs can pass thru single one 16:1 MUX,  Using the same metal for inputs (should be M3, Vertically. ) The overall size should be bigger than version_1, but it might decrease the complexity of global routing.  The floorplan would be a little bit different. 16:1 MUX X 11bits

Some Global Routing Issues  The outputs of Shift Registers are not fit the inputs of 2:1 MUX  It may waste some areas when we route the wires between this two blocks

Tom’s FSM  Large blocks LVS, but not too significant, because they don’t have too much interconnect  What is significant is wiring it all together  Floorplan done for wiring the whole FSM together  Inputs from bottom, outputs bottom or left

Tom’s FSM

Layout for Light Control FSM  All blocks are connected together and try to make them as compact as possible.  Need some time to do another layout for counter reset to fit in light control FSM.  DRC and LVS clean.

FSM Next State Fatter and shorter. Waste some area for routing but make the whole FSM more compact. Previous Updated Height:85.86um Width:6.48um Height:46.26um Width:17.28um

FSM TOP Revised layout for light control FSM. Height=68.94,Weight= Need some time to fit counter reset block into the FSM to make it more compact.

FSM TOP More detail in the layout. (Some additional lines are used for passing LVS) DRC and LVS clean. User defined inputs Global signals CLK,RESET etc. Inputs from previous FSM Outputs Combinational Part Sequential Part

Issue  Maybe I can use the counter reset block to fill the space to make it more compact. Need some time to modify it.  Maybe I should help others first before optimizing this FSM.

ALU Update  RCA Adder – 100%  DRC + LVS completed  Array Multiplier – 65%  Scrapped old one, too many wiring mistakes/missing many wire interconnects, seemed more efficient to work from scratch  What ’ s left?  A few more AND Gates connections to Full Adders  Only left enough room for 5-7 wires height wise … really need to get 12 wires(at worst) in there  Increasing Height => No, not going to double to height given Area is already close to initial estimate  Weird/Messy Wiring =>Yes, no otherway around it and it works  Attach HalfAdders+and to Array of Full adders+And  Bus wire around the array to inputs

RCA Adder(DRC + LVS Clean)

4xRow Full Adder(Array Mult) DRC=Clean LVS = Clean (minus AND Gates)

Close up on AND

Question ?