LoopBuster Hardware Loop Detection in Fast Mesh Ethernet Networks Uriel Peled and Tal Kol Guided by Boaz Mizrahi Advised by Gideon Kaempfer Digital Systems Laboratory Faculty of Electrical Engineering, Technion Winter 2007 – Winter 2008 Mid-Semester Presentation

LoopBuster Reminder Stop Ethernet Loops Without Tree Topology A B C LoopBuster

Presentation Outline Major Status Updates 1. Software Simulations Software simulation environment Parameter selection 2. General Architecture Block diagram 3. Board selection What’s Ahead? Re-visit the project timeline

Preliminary step before diving into hardware Implement algorithm in software Prove that it works in concept Simulate real traffic rates (2Gbps) and data Recordings from real networks (PCAP) Simulate connectivity to real computers Virtual stations using VMWare Live real stations (over Ethernet) Software Simulation Goals and Demands

Simulation Architecture Minimal HW Only 1 PC Written in C++ Fast 5K lines of code SW Timeline Supports any desired rate Flexible topology Choose the devices and how they connect

Parameter Selection Choose filter number and sizes For example: 13,12,10,10,9,9,8,8,7,7,6 Empirical selection with generic algorithm Genetic representation: filter size list Fitness function: memory size, false positives in SW simulation 3 levels of mutation Theoretical selection Mathematical probability analysis (occupancy problem) Numerical solution in C++ Surprisingly similar results (15%-30%)

Architecture Board Block Diagram

Architecture General Block Diagram

Network Stack Block Diagram

LoopBuster Array Block Diagram

LoopBuster Block Diagram

LoopBuster Control Block Diagram

Config and Statistics Block Diagram

Identify problematic board requirements Two 1Gbps Ethernet ports Try to rely on existing equipment Several alternatives explored Completely new board (~$1000) Daughter card for existing board (~$500) SFP modules for existing board (~$200) Develop daughter card (~$2000) Board Selection The Process

Board Selection Selected Board Memec FF1152 Xilinx Virtex-II Pro Existing in lab ($0) 2 SFP Modules 1Gbps Eth. RJ45 Buy (~$200) PCS/PMA Core Required for SFP Free from Xilinx ($0)

Project Milestones PRELIMINARY DESIGN software simulation(50), LB parameters(50), architecture(50), hardware design(50), hardware layout(50) 1/12/07 1/11/08 1/2/08 1/5/08 1/7/08 250hr 300hr 200hr 500hr DETAILED DESIGN micro architecture(100), logic implementation(100), logic simulation(100) PRODUCTION synthesis(100), circuit mechanics(50), circuit production(50) BRINGUP LB software driver(100), chip debug(200), circuit debug(100)

Status Today ( ) Completing preliminary design Starting micro architecture End-Semester Presentation Expecting middle of detailed design Micro architecture ready Logic implementation started