JTAG Course Lecturer: Tomer Rothschild BSDL Validation JTAG Course Lecturer: Tomer Rothschild

What’s the Problem? Did you ever test your code and discovered that the errors were as a result of faulty checks? The same problem is possible in BS tests too!

Agenda Introduction What’s the Problem? Inaccuracies in BSDL Files Validating the BSDL A Method for Basic BSDL Validation Asset & Agilent BSDL Validation Summary

Familiar?

Introduction The Boundary Scan Description Language (BSDL) is an IEEE language used to describe structures for boundary scan testing.

Introduction Automated Test Equipment tools read the BSDL files to understand the test resources available in the integrated circuit. Modern design tools are capable of generating a BSDL file automatically.

Agenda Inaccuracies in BSDL Files What’s the Problem? Introduction Validating the BSDL A Method for Basic BSDL Validation Asset & Agilent BSDL Validation Summary

Inaccuracies in BSDL Files Despite the fact that BSDL files are mostly created automatically, the process of creating them isn’t fault proof. IC designers may give the BSDL task low priority, and perhaps fail to give it the attention it demands. ICs often get revised after initial release, and their BSDL files don't get updated.

Syntactic & Semantic Inaccuracies BSDL files contain redundancy sufficient for automatic syntax and semantic verification. This kind of validation can be done regardless of the device under test. Moreover, the ATE’s that read the BSDL will inevitably recognize these errors.

Logical Inaccuracies The major pitfall is the logical errors. The ATE’s won’t recognize any errors of substance. This kind of errors will be the focus of the remainder of the lecture.

Examples of Consequences of Inaccuracies Mismatch between BSDL & silicon Consequences during board level test execution Port description Wrong pin function described Possible conflicts on board level interconnects; Pin might be diagnosed as open or stuck-at Boundary Scan Register description Wrong cell number assigned to port ATE is not exercising the correct pin, causing faulty diagnostic messages and maybe even conflicts between output drivers. (For a detailed table of mismatches and their consequences see [3])

Agenda Validating the BSDL What’s the Problem? Introduction Inaccuracies in BSDL Files Validating the BSDL A Method for Basic BSDL Validation Asset & Agilent BSDL Validation Summary

Validating the BSDL As we can see, it isn’t easy to debug faulty BSDL files, or even to know that they are faulty during the tests. It would, therefore, seem desirable to provide a way to Assess the accuracy of BSDL files prior to the tests.

Validating the BSDL We address the situation where a known good sample chip exists, and our task is to extract BSDL data directly from it. The proposed method works by stimulating and measuring pins of a sample IC.

Agenda A Method for Basic BSDL Validation What’s the Problem? Introduction Inaccuracies in BSDL Files Validating the BSDL A Method for Basic BSDL Validation Asset & Agilent BSDL Validation Summary

A Method for Basic BSDL Validation By applying a series of exploratory tests on the IC, we automatically extract the following: 1) The length of the IR 2) The length of the BSR 3) Pin mapping, order, and function 4) The identity of the BYPASS, EXTEST & SAMPLE/PRELOAD instructions 5) The identity of the IDCODE instruction and ID code, if present.

Extracting the Length of the IR Instruction length can be any number greater than or equal to 2. Nevertheless, we are able to assume a safe upper limit and denote it N. The algorithm is therefore: Go to state “shift IR” in the TAP controller FSM; Flush the register with N zeroes; Shift in ones (counting clocks all the while) until one appears at TDO.

Surprise! EXTEST & BYPASS Instructions Now that we have the length, we have two of the three essential instructions: BYPASS is defined in the standard as “all ones” EXTEST is defined as “all zeroes” 3 at the cost of 1!

Extracting the Length of the BSR We shall perform the same trick we did on the IR. This time we need to place the chip’s BSR between TDI and TDO. In order to achieve this, we shift and activate the newly-discovered EXTEST instruction.

Counting Patterns Our method finds the IC’s output pins and control cells, using “counting patterns”. These patterns have the following property of interest: Given a BSR we’ll denote its number of cells as C. Then we can successively load it with ceil(log2(C+2)) such patterns, and each cell in the register will undergo a unique series of state changes.

Counting Patterns Each cell in the BSR has a unique identifying number n. The first cell is numbered “l”, the second “2,” and so forth. 0 0 1 0 1 0 0 1 1

Extracting Pin Mapping, Order & Function We use the counting patterns to collect pin activity information. Next, we analyze the data collected in the previous step to determine which cells are output control cells, which cells they control, and the sign of that control. Finally, our method maps the output data cells to the pins of the IC. (For a more detailed algorithm of the pin information extraction see [1])

Extracting the SAMPLE/PRELOAD instruction In this stage, our method conducts a somewhat blind search. We potentially try every possible instruction value, except for the EXTEST & BYPASS instructions. Each candidate instruction is simply tested to see whether or not it behaves like a SAMPLE/PRELOAD instruction.

Extracting the IDCODE Instruction & ID code, if Present The trick here is in knowing how to find out if the ID code is present: when the TAP controller is reset and then advanced to the Shift-DR state without loading an instruction, the selected data register is either the BYPASS register or the 32-bit ID code register.

Extracting the IDCODE Instruction & ID code, if Present All that’s left is to fetch the ID code and try all instruction codes until we find one that outputs the ID code.

Agenda Asset & Agilent BSDL Validation What’s the Problem? Introduction Inaccuracies in BSDL Files Validating the BSDL A Method for Basic BSDL Validation Asset & Agilent BSDL Validation Summary

Don’t re-invent the wheel! Asset & Agilent BSDL Validation Asset & Agilent had recently opened a web based BSDL validation service. The service includes: Free BSDL Compilation – syntactic & semantic validation. Free Automatic Test Pattern Generation – generates test patterns that can be run in your simulator. BSDL Silicon Validation – an extensive logical validation. Requires shipping of the IC to Asset. http://www.asset-intertech.com/bsdl_service/

Summary BSDL files accuracy is extremely important - saves time and trouble debugging errors that don’t exist. Given a good sample IC, we learned a method to assess the core logic of BSDL files. High-quality validation services are currently available by leading companies (such as Asset).

Any Questions?

References http://www.google.com/url?sa=U&start=1&q=http://ieeexplore.ieee.org/iel3/4046/11600/00529884.pdf%3Farnumber%3D529884&e=9797 http://www.google.com/url?sa=U&start=3&q=http://ieeexplore.ieee.org/xpls/abs_all.jsp%3Fisnumber%3D28462%26arnumber%3D1271193%26count%3D32%26index%3D3&e=9797 http://www.google.com/url?sa=U&start=1&q=http://www.huntron.com/support/pdf/bsdl-lowcost.pdf&e=9797