9/18/08 Lab 2 - Solution TA: Jorge

9/18/08 Half-adder

9/18/08 Half-adder Testbench

9/18/08 Waveform for half-adder simulation tb stimulus 10 ns testbench ha x_signal y_signal x y s c s_signal c_signal

9/18/08 Full-adder

9/18/08 Full-adder Testbench

9/18/08 Waveform for full-adder simulation tb testbench fa x_signal y_signal x y s c s_signal c_signal z_signal z

9/18/08 Process. Type of processes. Process with sensitivity list. Process with wait statement. Example. Sequential Signal Assignment Statement. Syntax. Examples. Pitfall. Intermediate value. Conceptual implementation Variables. Syntax. Intermediate value. Example. Conceptual implementation Case statement. Syntax. Example. Multiplexor. Conceptual implementation. Lab 3 - Sequential Statements

9/18/08 Process Contains a set of sequential statements to be executed sequentially The whole process is a concurrent statement Can be interpreted as a circuit part enclosed inside of a black box Two types: with sensitive list and with wait statement Lab 3 - Sequential Statements

9/18/08 A process with a sensitivity list Syntax process (sensitivity_list) declarations; begin sequential statement;... end process; Lab 3 - Sequential Statements

9/18/08 Lab 3 - Sequential Statements Process with sensitivity list. Interpretation: “black box, indivisible circuit part”. Sensitivity list The execution of the process is initiated whenever an event occurs on any of the signals in the sensitivity list For practical purposes, you can regards a process as a “big” concurrent signal assignment statement Note:

9/18/08 Waveform for Example Process not activated on B change

9/18/08 A Process With wait Statement Process has no sensitivity list Process continues the execution until a wait statement is reached and then suspended Forms of wait statement: –wait on signals; –wait until boolean_expression; –wait for time_expression;

9/18/08 Sequential Signal Assignment Statement Signal_name <= value_expression; Syntax: U 0 1 U 1 0 U 1 1 U undefined

9/18/08 Sequential Signal Assignment Statement If all assignments are within DELTA-delay, only the last assignment takes effect. You can think as the signals are not updated until the end of the process (i.e., it never assumes any “intermediate” value). DELTA-delay: Default signal assignment propagation delay if no delay is explicitly prescribed VHDL signal assignments do not take place immediately Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at a future time

9/18/08 Variable Assignment Statement Variable_name := value_expression; Syntax: Used inside processes. The assignment takes effect “immediately”. Easy to understand, but not clear hardware mapping! Use signal always you can; rely on variables only for the characteristics that cannot be described by signals Note: Conceptual implementation

9/18/08 Case Statement Syntax: Example:

9/18/08 Introduction to Multiplexers Example of case statement: Multiplexor Truth Table

9/18/08 4-to-1 multiplexer – VHDL Implementation Entity ENTITY mux4x1 IS PORT ( S : IN STD_LOGIC_VECTOR (1 downto 0); D0 : IN STD_LOGIC; D1 : IN STD_LOGIC; D2 : IN STD_LOGIC; D3 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mux4x1; ARCHITECTURE multiplexor4x1 OF mux4x1 IS BEGIN PROCESS(S, D0, D1, D2, D3) BEGIN CASE S IS WHEN "00" => Y <= D0; WHEN "01" => Y <= D1; WHEN "10“ => Y <= D2; WHEN OTHERS => Y <= D3; END CASE; END PROCESS; END multiplexor4x1; Architecture