8/29/06 and 8/31/06 ELEC / Lecture 3 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage Low Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

8/29/06 and 8/31/06ELEC / Lecture 32 Capacitances In Out C1C1 C2C2 V DD GND CWCW

8/29/06 and 8/31/06ELEC / Lecture 33 Miller Capacitance In Out C1C1 C2C2 V DD GND CWCW CMCM

8/29/06 and 8/31/06ELEC / Lecture 34 Before Transition In Out C1C1 C2C2 V DD GND CWCW CMCM 0 +V DD

8/29/06 and 8/31/06ELEC / Lecture 35 After Transition In Out C1C1 C2C2 V DD GND CWCW CMCM 0 -V DD Energy from supply = 2 C M V DD 2 Effective capacitance = 2 C M from pullup devices of previous gate

8/29/06 and 8/31/06ELEC / Lecture 36 Capacitances in MOSFET SourceDrain Gate oxide Gate Bulk CsCs CdCd CgCg C gd C gs

8/29/06 and 8/31/06ELEC / Lecture 37 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

8/29/06 and 8/31/06ELEC / Lecture 38 Gate Capacitance C g = C ox WL = C 0, intrinsic cap. C g = C permicron W ε ox C permicron =C ox L=── L t ox where ε ox = 3.9ε 0 for Silicon dioxide = 3.9×8.85× F/cm

8/29/06 and 8/31/06ELEC / Lecture 39 Intrinsic Capacitances Capacitance Region of operation CutoffLinearSaturation Cgb C0C0C0C000 Cgs0 C 0 /2 2/3 C 0 Cgd0 C 0 /2 0 Cg = Cgs+Cgd+Cgb C0C0C0C0 C0C0C0C0 2/3 C 0 Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.

8/29/06 and 8/31/06ELEC / Lecture 310 Low-Power Transistors Device scaling to reduce capacitance and voltage. Device scaling to reduce capacitance and voltage. Body bias to reduce threshold voltage and leakage. Body bias to reduce threshold voltage and leakage. Multiple threshold CMOS (MTCMOS). Multiple threshold CMOS (MTCMOS). Silicon on insulator (SOI) Silicon on insulator (SOI)

8/29/06 and 8/31/06ELEC / Lecture 311 Device Scaling Reduced dimensions Reduced dimensions Reduce supply voltage Reduce supply voltage Reduce capacitances Reduce capacitances Reduce delay Reduce delay Increase leakage due to reduced V DD / V th Increase leakage due to reduced V DD / V th

8/29/06 and 8/31/06ELEC / Lecture 312 A Simplistic View Assume: Assume: Dynamic power dominates Dynamic power dominates Power reduces as square of supply voltage; should reduce with device scaling Power reduces as square of supply voltage; should reduce with device scaling Power reduced linearly with capacitance; should reduce with device scaling Power reduced linearly with capacitance; should reduce with device scaling Delay is proportional to RC time constant; R is constant with scaling, RC should reduce Delay is proportional to RC time constant; R is constant with scaling, RC should reduce Power reduces with scaling Power reduces with scaling

8/29/06 and 8/31/06ELEC / Lecture 313 Simplistic View (Continued) What if voltage is further reduced below the constant electric field value? What if voltage is further reduced below the constant electric field value? Will power continue to reduce? Yes. Will power continue to reduce? Yes. Since RC is independent of voltage, can clock rate remain unchanged? Since RC is independent of voltage, can clock rate remain unchanged? Answer to last question: Answer to last question: Yes, if threshold voltage was zero. Yes, if threshold voltage was zero. No, in reality. Because higher threshold voltage will delay the beginning of capacitor charging/discharging. No, in reality. Because higher threshold voltage will delay the beginning of capacitor charging/discharging.

8/29/06 and 8/31/06ELEC / Lecture 314 Consider Delay of Inverter In Out V DD GND C R t B Charging of C begins

8/29/06 and 8/31/06ELEC / Lecture 315 Idealized Input and Output t f V th t B t B 0.5V DD V DD time 0.69CR INPUT OUTPUT Gate delay t B = t f V th /V DD 0.5V DD

8/29/06 and 8/31/06ELEC / Lecture 316 Gate Delay For V DD >V th Gate delay=(t f V th /V DD ) RC – 0.5 t f =t f (V th /V DD – 0.5 ) RC For V DD ≤V th Gate delay=∞

8/29/06 and 8/31/06ELEC / Lecture 317 Approx. Gate Delay vs. V DD 0.69RC 0.5t f Gate delay V DD /V th

8/29/06 and 8/31/06ELEC / Lecture 318 Power - Delay vs. V DD 0.69RC 0.5t f Gate delay V DD /V th Power With leakage

8/29/06 and 8/31/06ELEC / Lecture 319 Optimum Threshold Voltage V DD / V th Delay or Energy-delay product Delay Energy-delay product V th = 0.7V V th = 0.3V

8/29/06 and 8/31/06ELEC / Lecture 320 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd

8/29/06 and 8/31/06ELEC / Lecture 321 Transistor in Cut-Off State +-+- V g < Polysilicon gate SiO 2 p-type body

8/29/06 and 8/31/06ELEC / Lecture 322 Threshold Voltage, V th < V g < V th Depletion region Polysilicon gate SiO 2 p-type body +-+- V g > V th Depletion region Polysilicon gate SiO 2 p-type body V th is a function of: Dopant concentration, Thickness of oxide

8/29/06 and 8/31/06ELEC / Lecture 323 α-Power Law Model α-Power Law Model V gs > V th and V ds > V dsat = V gs – V th (Saturation region): β I ds =P c ─ (V gs – V th ) α 2 whereβ=μC ox W/L, μ = mobility For fully ON transistor, V gs = V ds = V DD : β I dsat =P c ─ (V DD – V th ) α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp , 1990.

8/29/06 and 8/31/06ELEC / Lecture 324 α-Power Law Model (Cont.) V gs = 1.8V Shockley α-power law Simulation V ds I ds (μA) I dsat

8/29/06 and 8/31/06ELEC / Lecture 325 α-Power Law Model (Cont.) 0V gs < V th cutoff I ds =I dsat ×V ds /V dsat V ds < V dsat linear I dsat V ds > V dsat saturation V dsat =P v (V gs – V th ) α/2

8/29/06 and 8/31/06ELEC / Lecture 326 α-Power Law Model (Cont.) α = 2, for long channel devices or low V DD α = 2, for long channel devices or low V DD α ~ 1, for short channel devices α ~ 1, for short channel devices

8/29/06 and 8/31/06ELEC / Lecture 327 Power and Delay Power=CV DD 2 CV DD 1 1 Inverter delay=──── (─── + ─── ) 4 I dsatn I dsatp KV DD =─────── (V DD – V th ) α

8/29/06 and 8/31/06ELEC / Lecture 328 Power-Delay Product V DD 3 Power × Delay=constant ×─────── (V DD – V th ) α 0.6V1.8V3.0V V DD Power Delay

8/29/06 and 8/31/06ELEC / Lecture 329 Optimum Threshold Voltage For minimum power-delay product: 3V th V DD =─── 3 – α For long channel devices, α = 2, V DD = 3V th For very short channel devices, α = 1, V DD = 1.5V th

8/29/06 and 8/31/06ELEC / Lecture 330 Leakage IGIG IDID I sub I PT I GIDL n+ Ground V DD R

8/29/06 and 8/31/06ELEC / Lecture 331 Leakage Current Components Subthreshold conduction, I sub Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide Gate tunneling, I G through thin oxide

8/29/06 and 8/31/06ELEC / Lecture 332 Subthreshold Leakage V gs – V th Isub=I 0 exp( ───── ) nv th V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA V th Subthreshold region Saturation region

8/29/06 and 8/31/06ELEC / Lecture 333 Normal CMOS Inverter Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output VDD GND o

8/29/06 and 8/31/06ELEC / Lecture 334 Leakage Reduction by Body Bias Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output V BBp V DD GND V BBn V BBp o

8/29/06 and 8/31/06ELEC / Lecture 335 Body Bias, V BBn < V g < V th Depletion region Polysilicon gate SiO 2 p-type body +-+- V g < Polysilicon gate SiO 2 p-type body V t is a function of: Dopant concentration, Thickness of oxide

8/29/06 and 8/31/06ELEC / Lecture 336 Further on Body Bias Large body bias can increase gate leakage (I G ) via tunneling through oxide. Large body bias can increase gate leakage (I G ) via tunneling through oxide. Body bias is kept less than 0.5V. Body bias is kept less than 0.5V. For V DD = 1.8V For V DD = 1.8V V BBn = - 0.4V V BBn = - 0.4V V BBp = 2.2V V BBp = 2.2V

8/29/06 and 8/31/06ELEC / Lecture 337 Summary Device scaling down reduces supply voltage Device scaling down reduces supply voltage Reduced power Reduced power Increases delay Increases delay Optimum power-delay product by scaling down threshold voltage Optimum power-delay product by scaling down threshold voltage Threshold voltage reduction increases subthreshold leakage power Threshold voltage reduction increases subthreshold leakage power Use body bias to reduce subthreshold leakage Use body bias to reduce subthreshold leakage Body bias may increase gate leakage Body bias may increase gate leakage