2015/6/10 Spring Lecture 1 The VLSI Design Problem Space © 2002 Dr. James P. Davis CSCE 491 Computer Engineering Design Project

Page 2© 2002 Dr. James P. Davis Lecture 1 - Outline Introduction to VLSI Systems Design (CSCE 613 Notes) VLSI-based Systems-On-a-Chip (SOC) Example: Wireless Communications The Widening Productivity Gap: Capacity vs. Capability VLSI Design as a State-space Search Problem The Cost Associated with Design Decision-making Strategies for Minimizing Cost: Abstract Modeling and Rapid Iteration Example: Transmit-Receiver block FIR Filter CSCE 491 Course Curriculum Topics Instructional Method Design Project Execution Process

Page 3© 2002 Dr. James P. Davis CSCE 491 Course Curriculum Knowledge Source Lecture TopicsMethodology & Tools Design project processes & workflow System design process, process steps, and deliverables; design deliverable quality and “goodness” metrics; design tradeoff analysis; design workflow and tool chain. System design methods [Rozenblit et al., 1995]; Siemens metric set [Moller et al., 1994]; ASM design [Fletcher, 1980, Davis, 1995 & 1996], UML design [Rumbaugh et al., 1999]. Design project planning, issues mgmt. & reporting Project definition, planning and execution to plan; issues management; project notebooks; status and exception reporting; Project teams, team roles and role responsibilities. GO-CART planning method [Randolph et al., 1988]; MS-Project 2000; Report templates [Ernst & Young, 1996]; gIBIS issue management method [Conklin et al., 1988]. IEEE WLAN architecture & protocols OSI 7 Layer model; functions, architecture and abstract models; MAC layer; b PHY layer (time permitting). Course text [O’Hara et al., 1999]; OSI abstraction [Tanenbaum, 1981]; IEEE Working Group Notes. Course Project Activities Project scope, milestones & deliverables definition; design requirements and specification; system architecture analysis (UML); detailed design and analysis (ASM); high-level verification (FSM, Data path); VHDL or Verilog implementation; module- level design verification; Logic synthesis (time permitting); Integration and system test; project post-mortem and lessons learned. MS-Project 2000; Design Specification (to be created in Rational Rose as Use Cases and Sequence Diagrams) with design criteria as annotated text; IEEE Requirements Standard; KBS’ flowHDL (integrated FSM and data path design), KBS’ blockHDL (partitioned module hierarchy and pin-out); ModelSim VHDL or Silos Verilog simulator (HDL function and timing verification); Protocol Emulator test harness (to be created).

Page 4© 2002 Dr. James P. Davis CSCE 491 Course Instruction Course Instructional Method: The approach to be taken in the presentation of the course materials and execution of the design project tasks is to follow an iterative model (based on Mitchell et al., model for learning systems). The believed benefits of such an approach are as follows: A better correlation between lectures and project “labs”. An easier process of evaluating student performance, as each design project task is being done, so as to assign grades to individual activities, and to give the student opportunity to learn from mistakes, and, A better means to insure that the students are getting the material through constant assignment, performance and evaluation, coupled with lectures.

Page 5© 2002 Dr. James P. Davis CSCE 491 Course Project Process Design Workflow-1: Project execution process Includes the activities carried out in parallel to create the b emulator functionality that will be used to evaluate system correctness, completeness and overall adherence to project specification.