Advanced Encryption Standard For Smart Card Security Aiyappan Natarajan David Jasinski Kesava R.Talupuru Lilian Atieno Advisor: Prof. Wayne Burleson

Outline  Recap - Aiyappan  System Interface - Aiyappan  Key Expansion - David  Encryption 1 - Lilian  Encryption 2 – Kesava  Future Work – Kesava

I/P Rdy_in Processor FSM EncryptKey Sched I/P FSM O/P FSM O/P 128 clk Reset clk Reset Ready O/P Request O/P start send clk Reset Key Sub key System Architecture Data/Key Reg. Module

Processor Finite State Machine The main controller for all the other modules Controlled by two signals Reset and start Gets instructions stored in the memory Decodes instructions Enables the appropriate signals

Input Controller Communicates with external system through a serial I/O pin Gets the input data and key from the external system Gives the 128-bit parallel data to data/key register module Controlled by processor

Data/Key register module Stores input data and key in the appropriate registers Controlled by processor through two control signals mux_en, d_k

Output Controller Sends the output data to the external system Controlled by processor Data transfer through serial I/O pin External communication through handshaking signals

ExternalSystem InputControllerFSM ProcessorFSM Data/Key Register Serial I/O send Rdy_inRdy_Out rec_data clkResetclk128 Parallel Data Reset Mux_end_k clk Data Key Processor – Input Controller Interface PC instr 2 3

Simulation Results

Simulation Results (contd.)

Processor - Output Controller Interface Encrypted Data ExternalSystem OutputControllerFSM ProcessorFSM Serial I/O clk 128 clk Send_data Data_rdy Reset sentOutput_data instrPC 2 3

Simulation Results

Work completed RTL code for all the modules Test bench for each module Simulation for each module Integrated the Processor, Data/key register, Input and Output controller Test bench for the integrated top module Simulation for the top module

Work to be done Integrate the Encryption core and Key scheduling core along with the interface Test Bench for the entire interface Synthesize each module Simulation for synthesized netlist Synthesize the total integrated module Simulation for the entire system

Key Expansion Outline  Reminder of what Key Expansion is  Update on the progress in this module  Update on what still needs to be done

Key Scheduling  Input: 128 bit Key  Output: 1408 bit Expanded Key  Process: –Word rotation –Look up Tables –XOR operations

Completed Work  Behavioral Model (~481 lines of verilog code)  RTL code (~422 lines of verilog code)  Synthesized RTL code (~30,000 gates) –With warnings  Error Propagation

Behavioral Functionality

Synthesized Design

Error Propagation

What Needs to Be Done  Power Analysis  Gate Level Timing Analysis  Design Optimization

ShiftRow() Transformation bit data is broken down into four rows -Each of the 32-bit rows contains 4 bytes. -The first row is not shifted. -The last three rows of the State are byte-wise cyclically shifted as shown in the next slide.

no shift

Mix column() Transformation - Operates on State column-by-column. - Each column is treated as a four-term polynomial. -The four bytes in the four “rows” are used for matrix multiplication in GF(2 8 ) as shown below.

BLOCK DIAGRAM FOR MIX COLUMN Left shift by 1 bit x1 XOR

Key Add SubstitutionShift RowMix ColumnKey Add SubstitutionShift RowKey Add Sub Key ED Raw Data Encryption Algorithm Flow Sub Key Repeat (Round-1) times

Sub_bytes Transformation SSS SSS …… Input Output

Add Round key Operation ABC D E F G H I J K L M N O P A1 B1 C1 D1 E1 F1 G1 H1 I1 J1 K1 L1 M1 N1 O1 P1 A2 B2 C2 D2 E2 F2 G2 H2 I2 J2 K2 L2 M2 N2 O2 P2 = StateKey Output

State Diagram for Encryption Algorithm S0 S2 S3 S1 Count=1 Count=2 Repeat until Count =10 Count=11 Roll back to S0

Future Work  Integrate all modules  Synthesize all modules  Power Estimation for the integrated system  Repeat all previous steps for the Decryption module