Using State Machines as Control Circuits Lecture L9.4.

Slides:

Advertisements

Similar presentations

Modulo-N Counters Module M10.4 Section 7.2.

Advertisements

Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN

Shift Registers Module M11.1 Section 7.3.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

Magnitude Comparator Lecture L6.4 Section 6.1.

Counters. In class excercise How to implement a “counter”, which will count as 0,3,1,4,5,7,0,3,1,…… Q2Q1Q0D2D1D

1 EE121 John Wakerly Lecture #10 Some shift-register stuff Sequential-circuit analysis.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp

Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)

Multiplexers Lecture L6.4 Section 6.4.

Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.

Designing State Machines Lecture L9.2 Handout Section 9.2.

Datapaths Lecture L10.2 Sections 10.2, ALU (Sect. 7.5 and Lab 6)

Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Counters as State Machines Lecture L9.1 Handout Section 9.1.

Designing State Machines SQRT controller Lecture L9.2a Section 9.2.

Equality Detector Lecture L6.1 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

Flip-Flops Module M10.2 Section 7.1. D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

Binary Counters Lecture L8.3 Section 8.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

Shifter Lecture L7.4 Group HW #4 Section 10.3.

Modulo-N Counters Lecture L8.4 Section 7.2. Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter.

Codes and Code Converters

Code Converters Module M7.1 Section 6.5. Code Converters Binary-to-BCD Converters ABEL TRUTH_TABLE Command.

Arbitrary Waveforms Module M10.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Arithmetic Logic Unit (ALU) Lecture L7.5 Section 7.5.

Pulse-Width Modulated DAC Lecture 11.3 Section 11.5.

Multiplexers Module M6.1 Section 6.4. Multiplexers A 4-to-1 MUX TTL Multiplexer A 2-to-1 MUX.

2’s Complement 4-Bit Saturator

Adders Lecture L7.1 Section 6.2 Section 10.4 (pp )

Shifters Lecture L7.4 Section 7.4. MODULE shift TITLE 'shifter' DECLARATIONS " INPUT PINS " D3..D0 PIN 11,7,6,5; D = [D3..D0]; s2..s0 PIN 3,2,1; S.

Arbitrary Waveform Discussion 12.2 Example 34. Recall Divide-by-8 Counter Use q2, q1, q0 as inputs to a combinational circuit to produce an arbitrary.

Flip-Flops Lecture L8.2 Section 8.1. Recall the !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0.

Decoders Module M9.1 Section 6.3. Decoders TTL Decoders.

Arithmetic Logic Unit (ALU) Lecture L9.3 Lab 10. ALU CB = carry_borrow flag Z = zero flag (Z = 1 if Y = 0)

Shift Registers Lecture L6.6 Section Bit Shift Register.

Equality Detector Lecture L6.3 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

7-Segment Displays Module M7.2 Section 6.5. Turning on an LED Common Anode.

Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.

FSMs in Verilog and other random things 9/27/02. FSM structure CLK STATE Next State Logic Inputs Output Logic Outputs.

Lab 6 Module M8.3. EXPERIMENT 6: Adder/Subtractor PRE-LAB 1.Read and understand text Sec. 6.2, Adders and Subtractors, pages Using textbook.

Department of Communication Engineering, NCTU 1 Unit 2 Reviews on Logic Elements.

Counters. In class excercise How to implement a “counter”, which will count as 0,3,1,4,5,7,0,3,1,…… Q2Q1Q0D2D1D

Traffic Lights Discussion D8.3a. Recall Divide-by-8 Counter Use Q2, Q1, Q0 as inputs to a combinational circuit to produce an arbitrary waveform. s0 0.

EE121 John Wakerly Lecture #11

A Greatest Common Divisor (GCD) Processor Lecture L10.3 Sections 10.4, 10.5.

EE121 John Wakerly Lecture #9

CEC 220 Digital Circuit Design Dice Game Wed, April 06 CEC 220 Digital Circuit Design Slide 1 of 15.

Logiske funktioner i Peel. PEEL 18CV8 logic diagram.

CSE 140 Lecture 15 System Design II CK Cheng CSE Dept. UC San Diego 1.

Digital Logic & Design Dr. Waseem Ikram Lecture No. 35.

Digital Logic & Design Dr. Waseem Ikram Lecture 37.

Digital Logic & Design Dr. Waseem Ikram Lecture 39.

Magnitude Comparator Module M5.2 Section 6.1.

Overview Instruction Codes Computer Registers Computer Instructions

Simple Processor Control Unit

CSE 140 Lecture 16 System Designs

Jeremy R. Johnson Mon. Apr. 3, 2000

Counters as State Machines

Digital Logic & Design Dr. Waseem Ikram Lecture No. 34.

Shift Registers Lecture L8.6 Section 8.3.

Designing Digital Circuits Using Hardware Description Languages (HDLs)

Finite State Machines.

Register-Transfer Level Components in Verilog

Digital Logic & Design Dr. Waseem Ikram Lecture No. 36.

Magnitude Comparator Lecture L6.2 Section 6.1.

CSE 140 Lecture 16 System Designs

Presentation transcript:

Using State Machines as Control Circuits Lecture L9.4

Using State Machines as Control Circuits Designing a Game: Simon-nomiS Implementing Simon-nomiS using ABEL

Simon-nomiS

Iteration Counter, C

Simon-nomiS

SIMON-NOMISSIMON-NOMIS

Using State Machines as Control Circuits Designing a Game: Simon-nomiS Implementing Simon-nomiS using ABEL

MODULE SimonnomiS TITLE 'Simon-nomiS - A twisted game of the traditional Simon' DECLARATIONS " INPUT PINS " PB PIN 74; " push-button switch SW1 (clock) clear PIN 70;" push-button switch SW2 [R,Y,B,G] PIN 4,3,2,1;"Switches S7:1-4 I = [R,Y,B,G]; " OUTPUT PINS " O3..O0 PIN 40,41,43,44 ISTYPE 'com'; " LED O = [O3..O0]; " 4-bit output vector Q3..Q0 NODE istype 'reg'; Q = [Q3..Q0]; C2..C0 NODE istype 'reg'; C = [C2..C0]; Simon.abl Iteration counter

" Definitions QSTATE = [Q3, Q2, Q1, Q0]; ShowRed = [0, 0, 0, 0]; ShowBlue = [0, 0, 0, 1]; ShowGreen = [0, 0, 1, 0]; ShowYellow = [0, 0, 1, 1]; UserInput1 = [0, 1, 0, 0]; UserInput2 = [0, 1, 0, 1]; UserInput3 = [0, 1, 1, 0]; UserInput4 = [0, 1, 1, 1]; LostGame = [1, 0, 0, 0]; WonGame = [1, 0, 0, 1]; Simon.abl (cont.)

state_diagram QSTATE state ShowRed: if C == 0 then UserInput1 with C := 1; else ShowBlue with C := C; state ShowBlue: if C == 1 then UserInput2 with C := 2; else ShowGreen with C := C; state ShowGreen: if C == 2 then UserInput3 with C := 3; else ShowYellow with C := C; state ShowYellow: goto UserInput4;

state UserInput1: if (I == 8) & (C == 4) then WonGame with C := 0 else if I == 8 then ShowRed with C := C; else LostGame; state UserInput2: if I == 2 then UserInput1 with C := C else LostGame; state UserInput3: if I == 1 then UserInput2 with C := C else LostGame; state UserInput4: if I == 4 then UserInput3 with C := C else LostGame; state WonGame: goto WonGame; state LostGame: goto LostGame; Simon.abl (cont.)

16; WHEN QSTATE == ShowRed then O = 8; ELSE WHEN QSTATE == ShowBlue then O = 2; ELSE WHEN QSTATE == ShowGreen then O = 1; ELSE WHEN QSTATE == ShowYellow then {O = 4; C := 4;} ELSE WHEN QSTATE == WonGame then {O = 0F; C := 0;} ELSE WHEN QSTATE == LostGame then {O = 9; C := C;} ELSE O = 0; Q.C = PB; Q.AR = clear; C.C = PB; C.AR = clear; Remember – O is combinational – C is registered Simon.abl (cont.) Output O is a function of the state

test_vectors([PB,clear,I] -> [Q,C,O]) [.c.,1,.X.] -> [0,0,8]; [.c.,0,.X.] -> [4,1,0]; [.c.,0,8] -> [0,1,8]; [.c.,0,.X.] -> [1,1,2]; [.c.,0,.X.] -> [5,2,0]; [.c.,0,2] -> [4,2,0]; [.c.,0,8] -> [0,2,8]; [.c.,0,.X.] -> [1,2,2]; [.c.,0,.X.] -> [2,2,1]; [.c.,0,.X.] -> [6,3,0]; [.c.,0,1] -> [5,3,0]; [.c.,0,2] -> [4,3,0]; [.c.,0,8] -> [0,3,8]; [.c.,0,.X.] -> [1,3,2]; [.c.,0,.X.] -> [2,3,1]; [.c.,0,.X.] -> [3,3,4]; [.c.,0,.X.] -> [7,4,0]; [.c.,0,4] -> [6,4,0]; [.c.,0,1] -> [5,4,0]; [.c.,0,2] -> [4,4,0]; [.c.,0,8] -> [9,0,0F]; "--winning [.c.,0,.X.] -> [9,0,0F]; "--winning "[.c.,0,4] -> [8,0,9]; "[.c.,0,.X.] -> [8,0,9]; " -- replace the last two with the two " -- above for Losing a game END SimonnomiS Simon.abl (cont.)