GROUP MEMBERS TU NGUYEN DINH LE

4 bit Parallel input to serial output (4bit_PISO) shift REG.

Design Flow Design specification Schematic capture Create symbol TestBench

Design specification Use minimum size of CMOS transistors Use 2input nand gate to create DFF and 4bit PISO. Clock running at 25MHz per cycle = 40n second/cycle. Max. Power is 500 mW Area is no more than 40 mil^2 Number of transistors used = 118 transistors => area = micro m^2 Number of 2Nand gates used = 26 Number of Inverter used = 7 Cap_load = 100f F Assume scale factor = 1

Schematic capture & Create symbol

2nand_testbench

DFF Symbol

Internal ckt of DFF

DFF_Layout

DFF Etracted

DFF_Testbench

4bit PISO shift REG.

LAYOUT PISO

Extracted

4 bit PISO

4bit_PISO_testbench

CONCLUSION The project has many errors; the layout of PISO has not done yet. The logic simulation of the PISO has errors We are having a trouble of managing the time (clock) The PISO need to be modified