Quine-McClusky Minimization Method Module M4.3 Section 5.3.

Slides:

Advertisements

Similar presentations

Glitches & Hazards.

Advertisements

CSEE 4823 Advanced Logic Design Handout: Lecture #2 1/22/15

Figure 4.1. The function f (x1, x2, x3) =  m(0, 2, 4, 5, 6).

Combinational Logic Circuits Chapter 2 Mano and Kime.

ELEC Digital Logic Circuits Fall 2008 Logic Minimization (Chapter 3) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

Quine-McCluskey (Tabular) Minimization  Two step process utilizing tabular listings to:  Identify prime implicants (implicant tables)  Identify minimal.

CS2100 Computer Organisation K-maps: Finding PIs and EPIs (AY2014/5) Semester 2.

ITEC 352 Lecture 4 Boolean logic / Karnaugh Maps.

4.2 Strategy for minimization So far, we used an intuitive approach to decide how the 1s in the K-map should be grouped together to obtain the minimum-cost.

بهينه سازي با روش Quine-McCluskey

Boolean Algebra.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 -Part 8.

Karnaugh Maps Discussion D6.2 Section Karnaugh Maps Minterm X Y F m m m m X Y F(X,Y) = m0 | m2 | m3 =  (0,2,3)

CMPE100 – Logic Design Tracy Larrabee – Winter ‘08 CE 100 Intro to Logic Design Tracy Larrabee –3-37A E2 (9-3476) –

Lecture Six Chapter 5: Quine-McCluskey Method Dr. S.V. Providence COMP 370.

SYEN 3330 Digital Systems Jung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 6.

Give qualifications of instructors: DAP

Quine-McClusky Minimization Method Discussion D3.2.

Example: Given a 4-bit input combination N=N 3 N 2 N 1 N 0, this function produces a 1 output for N=1,2,3,5,7,11,13, and 0 otherwise.  According to the.

ENEE244-02xx Digital Logic Design Lecture 10. Announcements HW4 assigned, due 10/9.

CS 140 Lecture 5 Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 5 Professor CK Cheng CSE Dept. UC San Diego 1.

Combinational Logic Circuits Chapter 2 Mano and Kime.

EECC341 - Shaaban #1 Lec # 7 Winter Combinational Circuit Minimization Canonical sum and product logic expressions do not provide a circuit.

Two Level Logic Optimization. Two-Level Logic Minimization PLA Implementation Ex: F 0 = A + B’C’ F 1 = AC’ + AB F 2 = B’C’ + AB product term AB, AC’,

Prime Factors. What are they? All composite numbers can be written as the product of prime numbers. This product is known as the prime factorisation of.

Digital Logic & Design Vishal Jethava Lecture 12 svbitec.wordpress.com.

Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Two-Level Minimization II.

Quine-McCluskey Computer Organization I 1 March 2010 © McQuain Introduction Recall that the procedure we've seen for forming a Boolean function.

Chapter 3. Minimization of Switching Functions. Given a sw function f(x 1, x 2, …, x n ) and some cost criteria, find a representation of f which minimizes.

The covering procedure. Remove rows with essential PI’s and any columns with x’s in those rows.

Quine-McCluskey (Tabular) Minimization Two step process utilizing tabular listings to: Identify prime implicants (implicant tables) Identify minimal PI.

ECE 2110: Introduction to Digital Systems PoS minimization Don’t care conditions.

Karnaugh map minimization Basic Terms (1) minterm maxterm - a single 1 - a single 0 1. implicant

ECE 3110: Introduction to Digital Systems Symplifying Products of sums using Karnaugh Maps.

UM EECS 270 Spring 2011 – Taken from Dr.Karem Sakallah Logic Synthesis: From Specs to Circuits Implementation Styles –Random –Regular Optimization Criteria.

Two Level Networks. Two-Level Networks Slide 2 SOPs A function has, in general many SOPs Functions can be simplified using Boolean algebra Compare the.

Copyright © 2004 by Miguel A. Marin Revised McGILL UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING COURSE ECSE DIGITAL SYSTEMS.

2-1 Introduction Gate Logic: Two-Level Simplification Design Example: Two Bit Comparator Block Diagram and Truth Table A 4-Variable K-map for each of the.

Simplification of incompletely specified functions using QM Tech.

ECE2030 Introduction to Computer Engineering Lecture 8: Quine-McCluskey Method Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.

1 ECE2030 Introduction to Computer Engineering Lecture 8: Quine-McCluskey Method Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

ENEE244-02xx Digital Logic Design Lecture 12. Announcements HW4 due today HW5 is up on course webpage. Due on 10/16. Recitation quiz on Monday, 10/13.

Computer Engineering (Logic Circuits) (Karnaugh Map)

Karnaugh Maps ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

CS2100 Computer Organisation

Quine-McCluskey Algorithm Gautam Singh. Outline: step 1 Find Prime Implicants: 1)Find all the minterms and sort by number of 1 bits (these are implicants)

CHAPTER 3: PRINCIPLES OF COMBINATIONAL LOGIC

ELEC Digital Logic Circuits Fall 2015 Logic Minimization (Chapter 3) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and.

Prof. Hsien-Hsin Sean Lee

ECE/CS 352 Digital System Fundamentals1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 2 – Part 5 Tom Kaminski & Charles R. Kime.

Key Observation Adjacencies in the K-Map

1 Gate Level Minimization EE 208 – Logic Design Chapter 3 Sohaib Majzoub.

Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.

EECS 270 Lecture 10. K-map “rules” – Only circle adjacent cells (remember edges are adjacent!) – Only circle groups that are powers of 2 (1, 2,

Technical Seminar II Implementation of

Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and

Heuristic Minimization of Two-Level Logic

3-7 Other Two-level Implementations

A Brief Review of Factoring

Plotting functions not in canonical form

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Chapter 3 Gate-level Minimization.

Quine-McClusky Minimization Method

SYEN 3330 Digital Systems Chapter 2 – Part 6 SYEN 3330 Digital Systems.

Minimization of Switching Functions

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Presentation transcript:

Quine-McClusky Minimization Method Module M4.3 Section 5.3

Quine-McCluskey Method Tabular Representations Prime Implicants Essential Prime Implicants

Tabular Representations WX YZ F = X & Y # !W & Y & !Z # W & !Y & Z # !W & X !W & X 01-- !W & Y & !Z 0-10 X & Y -11- W & !Y & Z 1-01

Prime Implicants F = X & !Y & Z # !X & !Z # !X & Y Each product term is an implicant A product term that cannot have any of its variables removed and still imply the logic function is called a prime implicant.

Prime Implicants X YZ F = Y & !Z # X

Prime Implicants F = Y & !Z # X X YZ Minterm X Y Z F 0 O O O O O

Finding Prime Implicants O Step 1Step 2 (2,6) (4,5) (4,6) (5,7) (6,7) Step 3 (4,5,6,7) (4,6,5,7) All unchecked entries are Prime Implicants -10 Y & !Z 1-- X

Prime Implicants F = Y & !Z # X X YZ Minterm X Y Z F 0 O O O O O

Essential Prime Implicants WX YZ Find the essential prime implicants using the Q-M method.

Essential Prime Implicants WX YZ minterms

Finding Prime Implicants Step 1Step 2 (0,1) 000- (0,2) 00-0 (0,8) -000 (1,3) 00-1 (1,5) 0-01 (2,3) 001- (2,10) -010 (8,10) 10-0 (3,7) 0-11 (5,7) 01-1 (10,14) 1-10 (7,15) -111 (14,15) 111- Step 3 (0,1,2,3) 00-- (0,2,1,3) 00-- (0,2,8,10) -0-0 (0,8,2,10) -0-0 (1,5,3,7) 0--1 (1,3,5,7) Prime Implicants

Find Essential Prime Implicants Prime Implicant Covered minterms Minterms ,14 7,15 14,15 0,1,2,3 0,2,8,10 1,3,5,7 XX XX XX XX X X XXXX X XXX *

3 Prime Implicants WX YZ !W & Z W & X & Y !X & !Z F = !W & Z # W & X & Y # !X & !Z