CSE 670 Embedded System Design Using FPGAs Prof. Richard E. Haskell 115 Dodge Hall

CSE 670 – Winter 2004 Prerequisites: Undergraduate course in digital design Programming in a high-level language

CSE 670 – Winter 2004 Text: None required References: HDL Chip Design, Douglas J. Smith, Doone Publications, Logic and Computer Design Fundamentals, 3 rd Ed., by M. Morris Mano and Charles R. Kime, Prentice Hall, The Student's Guide to VHDL, by Peter J. Ashenden, Morgan Kaufmann Publishers, Inc., San Francisco, The Verilog Hardware Description Language, 3 rd Ed., by Donald E. Thomas and Philip R. Moorby, Kluwer Academic Publishers, Boston, 1996.

Course Contents 1.CPLDs and FPGAs 2.VHDL and Verilog 3.Simulation and Synthesis of VHDL and Verilog models 4.Modeling Combinational Logic Circuits 5.Modeling Sequential Logic Circuits 6.State Machines and Processors

Course Objectives By the end of the course you should be able to Model any combinational circuit using VHDL. Simulate VHDL designs using Active HDL. Synthsize VHDL designs to Xilinx FPGAs. Model registers and datapaths using VHDL. Implement control logic using a finite state machine in VHDL. Design a processor and implement it on a Xilinx FPGA. Complete an FPGA design project and present and demonstrate the results.

Labs Lab for this course is in Room 133, SEB. Get account at Lab available during class and at other times. First lab done individually. Other labs -- work in groups of 2-3. Group lab results presented in class.

Projects Each group will design an embedded system using a Xilinx FPGA. Each group will write a paper describing their project. Each group will give an oral presentation on their project.

Exams There will be two exams and no final. Project presentations and demonstrations Wednesday, April 21th, 7: :00 p.m.

Grading Labs15% Projects Overall design20% Written report10% Oral presentation 5% Exam 125% Exam 2 25% 100%

Office Hours Tues., Thurs., 2:30 - 3:30 p.m. Phone: Web site: click on VHDL and CSE 670