Digital Signal Processor (DSP) By Steve D. Wong (166/198A) Ervin Rosario-Figueroa (166/198A) Lana Dam Ivan Pierre-Louis Cuong Nguyen Spring 2003 San Jose State University Department of Electrical Engineering

Outline Introduction Introduction Specification Specification Project Purpose Project Purpose

Introduction Design of a 4-Bit Digital Signal Processor (DSP) using CMOS Logic. Design of a 4-Bit Digital Signal Processor (DSP) using CMOS Logic. DSP is composed of a Multiplier, D Flip Flop and a Subtractor. DSP is composed of a Multiplier, D Flip Flop and a Subtractor. Up/Down Counter will be used as a test vector for the system. Up/Down Counter will be used as a test vector for the system.

Specifications Functional Specification Functional Specification 4-Bit Multiplier 4-Bit Multiplier 4-Bit Full Subtractor 4-Bit Full Subtractor D Flip Flop D Flip Flop 4-Bit Up/Down Counter 4-Bit Up/Down Counter Technical Specifications Technical Specifications Design Wn & Wp = 3  m Design Wn & Wp = 3  m Power <= 0.25Watt Power <= 0.25Watt Clock Frequency << 200 MHz V DD = 5 Volts

Schematic (4-Bit Multiplier) Schematic Layout

Test Bench (4-Bit Multiplier)

Simulation (4-Bit Multiplier)

Layout (4-Bit Multiplier)

Extract (4-Bit Multiplier)

LVS (4-Bit Multiplier)

Schematic (4-Bit Subtractor)

Test Bench (4-Bit Subtractor)

Simulation (4-Bit Subtractor)

Layout (4-Bit Subtractor)

Extract (4-Bit Subtractor)

LVS (4-Bit Subtractor)

Schematic (D Flip Flop)

Test Bench (D Flip-Flop)

Simulation (D Flip Flop)

Layout (D Flip-Flop)

Extract (D Flip Flop)

LVS (D Flip Flop)

Schematic (Up/Down Counter)

Test Bench (Up/Down Counter)

Simulation (Up/Down Counter)

Layout (Up/Down Counter)

Extract (Up/Down Counter)

LVS (Up/Down Counter)