CS 140 Lecture 17 Professor CK Cheng 11/26/02. System Designs 1.Intro 2.Spec 3.Implementation.

Slides:

Advertisements

Similar presentations

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

Advertisements

1 CS 140L Lecture 8 System Design Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.

Monday, 11/11/02, Slide #1 CS 106 Intro to Comp. Sci. 1 Monday, 11/11/02  Questions? HW 04 due today at 5.  Today – Lists and an introduction to searching.

1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 5 Professor CK Cheng 10/10/02. Part I. Combinational Logic 1.Spec 2.Implementation K-map: Sum of products Product of sums.

CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch ) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation.

CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )

CS 140 Lecture 2 Combinational Logic CK Cheng 4/04/02.

CS 140 Lecture 11 Professor CK Cheng 5/09/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

1 CS 140 Lecture 19 Sequential Modules Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )

CS 140L Lecture 7 Professor CK Cheng 5/13/02. Announcements  State Assignment: Chapters 7.4.3, 7.7.3, kinds of coding: 1) Binary – [ log 2 n ]

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

1 CS 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 17 System Designs III Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 17 System Designs III Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 6: Other Types of Gates Professor CK Cheng 1.

CS 140 Lecture 18 Professor CK Cheng 6/04/02. Part IV. System Designs Algorithm: { Input X, Y type bit-vector, start type boolean; Local-Object A, B type.

CS 140 Lecture 12 Professor CK Cheng 11/07/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

CS 140 Lecture 6 Professor CK Cheng Tuesday 10/15/02.

CS 140 Lecture 14 Professor CK Cheng 11/14/02. Part II. Standard Modules A.Interconnect B.Operators. Adders Multiplier Adders1. Representation of numbers.

CK Cheng Tuesday 10/2/02 CS 140 Lecture 2. Part I. Combinational Logic I) Specification –a. Language –b. Truth Table –c. Boolean Algebra –d. Incompletely.

Lecture 1: Introduction to Digital Logic Design CK Cheng Thursday 9/26/02.

CS 140 Lecture 4 Combinational Logic: K-Map Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140L Lecture 7 Professor CK Cheng 11/12/02. Transformation between Mealy and Moore Machines Algorithm: 1) For each NS, z = S i, j create a state S.

CS 140 Lecture 18 Professor CK Cheng 12/3/02. Standard Sequential Modules 1.Register 2.Shift Register 3.Counter.

CS 140L Lecture 9 Professor CK Cheng 6/03/02. transistors modules sequential machine system 1.Adders, Muxes 2.F-Fs and counters 3.Finite State Machine.

CS 140L Lecture 1 Professor CK Cheng 3/31/02. CMOS Logic (3.2 – 3.6) Complementary Metal-Oxide Semiconductor.

Lecture 1: Introduction to Digital Logic Design CK Cheng Tuesday 4/1/02.

CS 140 Lecture 11 Professor CK Cheng 5/31/02. C1C2 CLK x(t) y(t) Sequential Network Implementation Mealy & Moore machine State Table  Netlist s(t) D(t)

CS 140 Lecture 6 Professor CK Cheng UC San Diego.

CS 140 Lecture 10 Professor CK Cheng 10/29/02. Part II. Sequential NetworkReminder 1.Flip flops 2.Specification 3.Implement Netlist  State Table  State.

CS 140 Lecture 8 Professor CK Cheng 10/22/02. Part II. Sequential Network 1.Flip-flops SR, D, T, JK, State Table Characteristic Eq. Q(t+1) = f(x(t), Q(t)).

CS 140L Lecture 7 Transformation between Mealy and Moore Machines Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 19 Professor CK Cheng 12/05/02. Sequential Machine Standard Modules Combinational Sequential System Designs.

CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.

CS 140 Lecture 7 Professor CK Cheng 10/17/02. Combinational Logic  Complete set of gates  Other types of gates 1)XOR 2)NAND / NOR 3)Block Diagram Transfers.

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 12 Circuit Analysis Procedure.

CSE 140 Lecture 15 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

Computer ArchitectureFall 2007 © August 29, 2007 Karem Sakallah CS 447 – Computer Architecture.

CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Lecture 13 Problems (Mano)

CS 461 – Oct. 12 Parsing Running a parse machine –“Goto” (or shift) actions –Reduce actions: backtrack to earlier state –Maintain stack of visited states.

CSE 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.

Digital Design with SM Charts

CSE 140 Lecture 15 System Design II CK Cheng CSE Dept. UC San Diego 1.

CSE 140 Lecture 13 System Designs

CSE 140 Lecture 14 System Designs

CSE 140 Lecture 14 System Designs

How many words can you make from

CSE 140 Lecture 16 System Designs

CSE 140 Lecture 15 System Designs

CSE 140 Lecture 17 System Design II

CS 140 Lecture 16 Professor CK Cheng 11/21/02.

CS 140L Lecture 6 Professor CK Cheng 5/05/02.

CSE 140 Lecture 14 System Design

CS 140 Lecture 19 Standard Modules

CSE 140 Lecture 16 System Designs II

Intro to Programming & Algorithm Design

CS 140 Lecture 6: Other Types of Gates

CS 140 Lecture 13 Professor CK Cheng 11/12/02.

CS 140L Lecture 7 Transformation between Mealy and Moore Machines

CS 140L Lecture 8 Professor CK Cheng 11/19/02.

System Controller Approach

CSE 140 Lecture 16 System Designs

Presentation transcript:

CS 140 Lecture 17 Professor CK Cheng 11/26/02

System Designs 1.Intro 2.Spec 3.Implementation

Given an algorithm, produce the data and control subsystems Algorithm: { Input X, Y type bit-vector, start type boolean; Local-Object A, B type bit-vector; Output Z type bit-vector, done type boolean; Wait: If start’ goto Wait; S1: A  X || B  Y|| done  0; S2: If B >= 0 goto S4; S3: B  -B; S4: If A >= B goto S6; S5: A  A + 1 || B  B-1 || goto S4; S6: Z  4 * A || done  1 || goto Wait; }

Data Subsystem Control Subsystem C 1-7 (A > B)B7B7 X Y start Z done Z = 4 Ceiling[ (X + |Y| )/ 2] if X< |Y| 4X otherwise 8 8 8

A  X B  Y B  -B A >= B A  A + 1 B  B – 1 Z  4A operation A  Load (X) B  Load (Y) B  CS (B) Comp (A, B) A  INC (A) B  DEC (B) Z  Load (A) Z  SHL (Z) control C 1 C 2 C 3 C 4 C 5 C 6 C 7

B A C2C2 C3C3 C5C5 C1C1 C4C4 X INC Comp Z Control Unit B C6C6 C7C7 CS DEC Y C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 start done

S0: S1: S2: S3: S4: S5: S6: S7: S8: If start’, goto S0, else goto S1 A  X || B  Y || done  0 || goto S2 If B’ goto S4, else goto S3 B  CS (B), goto S4 If k goto S6, else goto S5 A  INC (A), B  DEC (B), goto S4 Z  A goto S7 Z  SHL (z), goto S8 Z  SHL (z), done 1, goto S0 Designing the control unit

State Machine S0 S1 S2 S3 S4 S8 S7 S6 S5 k’ k B B’ start’ start

start’ S2 S3 B7B7’ S5 S6 S0 S1 S4 k k’ S7 S8