1 ROBDD’s represents a logic function by a graph (DAG). (many logic functions can be represented compactly - usually better than SOP’s)represents a logic.

Slides:



Advertisements
Similar presentations
Model Checking Lecture 4. Outline 1 Specifications: logic vs. automata, linear vs. branching, safety vs. liveness 2 Graph algorithms for model checking.
Advertisements

Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Planning based on Model Checking Dept. of Information Systems and Applied CS Bamberg University Seminar Paper Svetlana Balinova.
CS357 Lecture: BDD basics David Dill 1. 2 BDDs (Boolean/binary decision diagrams) BDDs are a very successful representation for Boolean functions. A BDD.
SYMBOLIC MODEL CHECKING: STATES AND BEYOND J.R. Burch E.M. Clarke K.L. McMillan D. L. Dill L. J. Hwang Presented by Rehana Begam.
MVI Function Review Input X is p -valued variable. Each Input can have Value in Set {0, 1, 2,..., p i-1 } literal over X corresponds to subset of values.
Faculty of Computer Science LCPC 2007 Using ZBDDs in Points-to Analysis Stephen Curial Jose Nelson Amaral Department of Computing Science University of.
Introduction Combining two frameworks
© 2011 Carnegie Mellon University Binary Decision Diagrams Part Bug Catching: Automated Program Verification and Testing Sagar Chaki September.
© 2011 Carnegie Mellon University Binary Decision Diagrams Part Bug Catching: Automated Program Verification and Testing Sagar Chaki September.
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
Binary Decision Diagrams. ROBDDs Slide 2 Example Directed acyclic graph non-terminal node terminal node What function is represented by the graph?
Spring 07, Feb 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams Vishwani D. Agrawal James.
DATE-2002TED1 Taylor Expansion Diagrams: A Compact Canonical Representation for Symbolic Verification M. Ciesielski, P. Kalla, Z. Zeng B. Rouzeyre Electrical.
ECE Synthesis & Verification - Lecture 18 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Word-level.
Boolean Functions and their Representations
Multi-Valued Input Two-Valued Output Functions. Multi-Valued Input Slide 2 Example Automobile features 0123 X1X1 TransManAuto X2Doors234 X3ColourSilverRedBlackBlue.
A New Approach to Structural Analysis and Transformation of Networks Alan Mishchenko November 29, 1999.
Rolf Drechlser’s slides used
ECE 665 – Computer Algorithms 1 ECE 665 Spring 2004 ECE 665 Spring 2004 Computer Algorithms Binary Decision Diagrams Implementation Issues Slides adopted.
1 CSEP590 – Model Checking and Automated Verification Lecture outline for July 16, 2003.
ECE Synthesis & Verification - Lecture 9b 1 ECE 697B (667) Fall 2004 ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Systems Boolean.
Taylor Expansion Diagrams (TED): Verification EC667: Synthesis and Verification of Digital Systems Spring 2011 Presented by: Sudhan.
Computation Engines: BDDs and SAT (part 1) 290N: The Unknown Component Problem Lecture 7.
ECE Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
 2001 CiesielskiBDD Tutorial1 Decision Diagrams Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA
ECE 667 Synthesis & Verification - BDD 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Binary Decision Diagrams (BDD)
ENGG3190 Logic Synthesis “Binary Decision Diagrams” BDDs Winter 2014 S. Areibi School of Engineering University of Guelph.
ECE 667 Synthesis and Verification of Digital Systems
IT University of Copenhagen Lecture 8: Binary Decision Diagrams 1. Classical Boolean expression representations 2. If-then-else Normal Form (INF) 3. Binary.
1 ROBDD’s represents a logic function by a graph (DAG). (many logic functions can be represented compactly - usually better than SOP’s)represents a logic.
By Tariq Bashir Ahmad Taylor Expansion Diagrams (TED) Adapted from the paper M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre,”Taylor Expansion Diagrams:
Logic Decomposition ECE1769 Jianwen Zhu (Courtesy Dennis Wu)
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2006 Serdar Taşıran.
Digitaalsüsteemide verifitseerimise kursus1 Formal verification: BDD BDDs applied in equivalence checking.
Athens 2004 Symposium on Innovation of Computer Science Curriculum in Higher Education Athens 2004 Decision Diagrams: Principles of Programming Dragan.
B. Alizadeh Advanced Logic Design (2008) 1 / 55 Decision Diagrams.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Binary Decision Diagrams.
Binary Decision Diagrams (BDDs)
BOOLEAN ALGEBRA Saras M. Srivastava PGT (Computer Science)
November,2000University of Southern California1 Introduction to Binary Decision Diagrams - Shesha Shayee K. Raghunathan.
Department of Computer Engineering
ECE Synthesis & Verification - Lecture 11 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
Modular Decomposition and Interval Graphs recognition Speaker: Asaf Shapira.
Week 11 - Wednesday.  What did we talk about last time?  Graphs  Euler paths and tours.
CS 267: Automated Verification Lecture 6: Binary Decision Diagrams Instructor: Tevfik Bultan.
Algorithmic Software Verification V &VI. Binary decision diagrams.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
Notes on Sequence Binary Decision Diagrams: Relationship to Acyclic Automata and Complexities of Binary Set Operations Shuhei Denzumi1, Ryo Yoshinaka2,
Agenda Review: –Planar Graphs Lecture Content:  Concepts of Trees  Spanning Trees  Binary Trees Exercise.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
Mathematical Preliminaries
ICS 252 Introduction to Computer Design Lecture 12 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS, Ohio University March 12, 1998.
Binary decision diagrams (BDD’s) Compact representation of a logic function ROBDD’s (reduced ordered BDD’s) are a canonical representation: equivalence.
BDDs1 Binary Tree Representation The recursive Shannon expansion corresponds to a binary tree Example: Each path from the root to a leaf corresponds to.
Boolean Functions 1 ECE 667 ECE 667 Synthesis and Verification of Digital Circuits Boolean Functions Basics Maciej Ciesielski Univ.
Standard & Canonical Forms COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum.
Binary Decision Diagrams Prof. Shobha Vasudevan ECE, UIUC ECE 462.
Chapter 11. Chapter Summary  Introduction to trees (11.1)  Application of trees (11.2)  Tree traversal (11.3)  Spanning trees (11.4)
IT 60101: Lecture #121 Foundation of Computing Systems Lecture 13 Trees: Part VIII.
How CTL model checking works
ECE 667 Synthesis and Verification of Digital Systems
Binary Decision Diagrams
Binary Decision Diagrams
Binary Decision Diagrams
A logic function f in n inputs x1, x2, ...xn and
Binary Decision Diagrams
Example: Verification
A logic function f in n inputs x1, x2, ...xn and
Presentation transcript:

1 ROBDD’s represents a logic function by a graph (DAG). (many logic functions can be represented compactly - usually better than SOP’s)represents a logic function by a graph (DAG). (many logic functions can be represented compactly - usually better than SOP’s) canonical form (important) (only canonical if an ordering of the variables is given)canonical form (important) (only canonical if an ordering of the variables is given) many logic operations can be performed efficiently on BDD’s (usually linear in size of result - tautology and complement are constant time)many logic operations can be performed efficiently on BDD’s (usually linear in size of result - tautology and complement are constant time) size of BDD critically dependent on variable orderingsize of BDD critically dependent on variable ordering

2 ROBDD’s Directed acyclic graph (DAG) one root node, two terminals 0, 1 each node, two children, and a variable Shannon co-factoring tree, except reduced and ordered (ROBDD) Reduced: – –any node with two identical children is removed – –two nodes with isomorphic BDD’s are merged Ordered: Co-factoring variables (splitting variables) always follow the same order x i 1 < x i 2 < x i 3 < … < x i n

3 Example Two different orderings, same function. a bb cc d 0 1 c+bd b rootnode c+d c d f = ab+a’c+bc’d a c d b 01 c+bd d+b b 1 0

4 Efficient Implementation of BDD’s (Reference: Brace, Rudell, Bryant - DAC 1990) Hash-Table: hash-fcn(key) = value hash value of key collisionchain

5 Efficient Implementation of BDD’s Strong canonical form: A “unique-id” is associated (through a hash table) uniquely with each element in a set. With BDD’s the set is the set of all logic functions. A BDD node is a function. Thus each function has a unique-id in memory. BDD is a compressed Shannon co-factoring tree. v 0 1 f fvfvfvfv fvfvfvfv

6 ROBDD Ordered BDD (OBDD) Input variables are ordered - each path from root to sink visits nodes with labels (variables) in ascending order. a cc b 0 1 ordered order = a,c,b Reduced Ordered BDD - reduction rules: 1.if the two children of a node are the same, the node is eliminated: f = cf + c’f 2.if two nodes have isomorphic graphs, they are replaced by one of them These two rules make it so that each node represents a distinct logic function. a b c c 0 1 notordered b

7 Theorem Theorem 1 (Bryant ) ROBDD’s are canonical Thus two functions are the same iff their ROBDD’s are equivalent graphs (isomorphic). Of course must use same order for variables.

8 Function is Given by Tracing All Paths to 1 Notes: By tracing paths to the 1 node, we get a cover of pairwise disjoint cubes.By tracing paths to the 1 node, we get a cover of pairwise disjoint cubes. The power of the BDD representation is that it does not explicitly enumerate all paths; rather it represents paths by a graph whose size is measures by its nodes and not paths.The power of the BDD representation is that it does not explicitly enumerate all paths; rather it represents paths by a graph whose size is measures by its nodes and not paths. A DAG can represent an exponential number of paths with a linear number of nodes.A DAG can represent an exponential number of paths with a linear number of nodes. Each node is given by its Shannon representation:Each node is given by its Shannon representation: f = af a +  af a F = b’+a’c’ = ab’+a’cb’+a’c’ all paths to the 1 node a c b f f a = b’ f a = cb’+c’

9Implementation Variables are totally ordered: If v < w then v occurs “higher” up in the ROBDD (call it BDD from now on). Definition 1: Top variable of a function f is a variable associated with its root node. Example: f = ab + a’bc + a’bc’. Order is (a < b < c). f a = b, f  a = b a b 01f b is top variable of f b 01 f reduced f does not depend on a, since f a = f  a. Each node is written as a triple: f = (v,g,h) where g = f v and h = f  v. We read this triple as: f = if v then g else h = ite (v,g,h) = vg+v ’ h v f 01 h g 10 f v g h mux v is top variable of f

10 ITE Operator ite operator can implement any two variable logic function. There are 16 such functions corresponding to all subsets of vertices of B 2 : TableSubset Expression Equivalent Form AND(f, g) fgite(f, g, 0) 0010f > g f  gite(f,  g, 0) 0011f ff 0100f < g  fgite(f, 0, g) 0101g gg 0110XOR(f, g) f  gite(f,  g, g) 0111OR(f, g) f + gite(f, 1, g) 1000NOR(f, g) f + gite(f, 0,  g) 1001 XNOR(f, g) f  gite(f, g,  g) 1010NOT(g)  gite(g, 0, 1) 1011f  g f +  gite(f, 1,  g) 1100NOT(f)  fite(f, 0, 1) 1101f  g  f + gite(f, g, 1) 1110NAND(f, g) fgite(f,  g, 1)

11 Unique Table - Hash Table Before a node (v, g, h ) is added to BDD data base, it is looked up in the “unique-table”. If it is there, then existing pointer to node is used to represent the logic function. Otherwise, a new node is added to the unique-table and the new pointer returned. Thus a strong canonical form is maintained. The node for f = (v, g, h ) exists iff(v, g, h ) is in the unique-table. There is only one pointer for (v, g, h ) and that is the address to the unique-table entry. Unique-table allows single multi-rooted DAG to represent all users’ functions: hash value of key collisionchain

12 Recursive Formulation of ITE v = top-most variable among the three BDD’s f, g, h

13 Recursive Formulation of ITE Terminal cases: (0, g, f ) = (1, f, g) = f ite (f, g, g) = g ite(f, g, h) ite(f, g, h) if(terminal case) { return result; return result; } else if(computed-table has entry (f, g, h )) { return result; return result; } else { let v be the top variable of (f, g, h ); let v be the top variable of (f, g, h ); f <- ite(f v, g v, h v ); f <- ite(f v, g v, h v ); g <- ite (f  v, g  v, h  v ); g <- ite (f  v, g  v, h  v ); if( f equals g ) return g; if( f equals g ) return g; R <- find_or_add_unique_table(v, f, g ); R <- find_or_add_unique_table(v, f, g ); insert_computed_table( {f, g, h }, R); insert_computed_table( {f, g, h }, R); return R; } } return R; } } The “insert_computed_table” is a cache table where ite results are cached.

14 Example I= ite (F, G, H) = (a, ite (F a, G a, H a ), ite (F  a, G  a, H  a )) = (a, ite (1, C, H ), ite(B, 0, H )) = (a, C, (b, ite (B b, 0 b, H b ), ite (B  b, 0  b, H  b )) = (a, C, (b, ite (1, 0, 1), ite (0, 0, D))) = (a, C, (b, 0, D)) = (a, C, J) Check: F = a + b G = ac H = b + d ite(F, G, H) = (a + b)(ac) +  a  b(b + d) = ac +  a  bd = ac +  a  bd F,G,H,I,J,B,C,D are pointers b 1 1 a F B 1 1 a G c 0 C 1 b H d D a I d J 1 C D

15 Computed Table Keep a record of (F, G, H ) triplets already computed by the ite operator in a hash-based cache ( “cache” table). This means that the collision chain is not used (if collision, old entry thrown away ). The above structure is wasteful since the BDD nodes and collision chain can be merged.

16 Better Implementation

17 Extension - Complement Edges Can combine by making complement edges 01G 01 GGGG two different DAGs 01G GGGG only one DAG using complement pointer

18 Extension - Complement Edges To maintain strong canonical form, need to resolve 4 equivalences: VV VV VV VV Solution: Always choose one on left, i.e. the “then” leg must have no complement edge.

19 Ambiguities in Cache Table Standard Triples: ite(F, F, G )  ite(F, 1, G ) ite(F, G, F )  ite(F, G, 0 ) ite(F, G,  F )  ite(F, G, 1 ) ite(F,  F, G )  ite(F, 0, G ) To resolve equivalences: ite(F, 1, G )  ite(G, 1, F ) ite(F, 0, G )  ite(  G, 1,  F ) ite(F, G, 0 )  ite(G, F, 0 ) ite(F, G, 1 )  ite(  G,  F, 1 ) ite(F, G,  G )  ite(G, F,  F ) 1. First argument is chosen with smallest top variable. 2. Break ties with smallest address pointer. Triples: ite(F, G, H )  ite (  F, H, G )  ite (F,  G,  H)  ite (  F,  H, G) Choose the one such that the first and second argument of ite should not be complement edges(I.e. the first one above).

20 Tautology Checking Tautology returns 0, 1, or NC (not constant). ITE_constant(F, G, H ) { if(trivial case) { return result (0,1, or NC); } else if (cache table has entry for (F, G, H )) { return result; } else { let v be the top variable of F, G, H ; R  ITE_constant(F v, G v, H v ); if(R = NC) { insert_cache_table({F, G, H }, NC); return NC; } E  ITE_constant(F  v, G  v, H  v ); if( R  E) { insert_cache_table({F, G, H }, NC); return NC; } insert_cache_table({F, G, H }, E); return E; } } Note: in computing ITE_constant, we set up a temporary cache-table for storing results of the ITE_constant operator. When done, we can throw away this table if we like.

21 Compose Compose is an important operation for building the BDD of a circuit. Compose(F, v, G ) : F(v, x)  F( G(x), x) Means substitute v = G(x) Compose(F, v, G) {(in F replace v with G ) if(top_var(F) > v ) return F; (because F does not depend on v) if(top_var(F) = v ) return ITE(G, F 1, F 0 ); R  compose(F 1, v, G ); E  compose(F 0, v, G ); return ITE(top_var(F), R, E); (note that we call ITE on this rather than returning (top_var(F), R, E). Why? ) } returning (top_var(F), R, E). Why? ) }Notes: 1. F 1 is the 1-child of F, F 0 the 0-child. 2. G, R, E are not functions of v. 3. If top_var of F is v, then ite (G, R, E ) does the replacement of v by G.

22 End of lecture 7

23 Multivalued Decision Diagrams(MDD’s) “BDD’s” for MV-functions There is an equivalent theory (canonical etc.) for MDD’s: Typically, we encode the multi-valued variable with log 2 (|P v |) binary variables and use unused codes as “don’t cares” in a particular way: v P v = (0,1,2,3,4) MDD package in VIS Encode in binaryEncode in binary Use regular (optimized) BDDUse regular (optimized) BDDPackage Interface keeps track ofInterface keeps track ofencoding

24 Sets and Graphs: With MDDs we can represent and manipulate general sets and graphs. Set:  characteristic function of set  ((f (v ) = 1)  (v  S  P v ))  ((f (v ) = 1)  (v  S  P v )) Graph: (set of edges)  ((f (x, y ) = 1)  (x, y ) is an edge in graph where x and y are multi- valued variables representing nodes in the graph.

25 Zero Suppressed BDD’s - ZBDD’s ZBDD’s were invented by Minato to efficiently represent sparse sets. They have turned out to be extremely useful in implicit methods for representing primes (which usually are a sparse subset of all cubes). Different reduction rules: BDD: eliminate all nodes where then edge and else edge point to the same node.BDD: eliminate all nodes where then edge and else edge point to the same node. ZBDD: eliminate all nodes where the then node points to 0. Connect incoming edges to else node.ZBDD: eliminate all nodes where the then node points to 0. Connect incoming edges to else node. For both: share equivalent nodes.For both: share equivalent nodes BDD: ZBDD:

26 Canonicity Theorem 2 (Minato) ZBDD’s are canonical given a variable ordering and the support set. x1x1x1x1 x2x2x2x2 01 BDD x3x3x3x3 1 ZBDD if support is x 1, x 2, x 3 1 ZBDD if support is x 1, x 2 Example: x1x1x1x1 x2x2x2x2 01 BDD x3x3x3x3 1 ZBDD if support is x 1, x 2, x 3 x1x1x1x1 x2x2x2x2 01 x3x3x3x3