Registers VHDL Tutorial R. E. Haskell and D. M. Hanna T2: Sequential Logic Circuits

An 8-bit register q(7 downto 0) clk clr load d(7 downto 0) reg

Register entity

architecture reg_arch of reg is begin process(clk, clr) begin if clr = '1' then q(i) <= " "; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end process; end reg_arch; Register architecture Infers a flip-flop for all outputs (q)

debounce entity entity debounce is port ( inp, clk, clr: in std_logic; outp: out std_logic ); end debounce; debounce inpoutp clk clr

clk inp delay1 delay3 delay2 outp debounce

clk inp delay1 delay3 delay2 outp

architecture rtl of debounce is signal delay1, delay2, delay3: std_logic; begin process(clk, clr) begin if clr = '1' then delay1 <= '0'; delay2 <= '0'; delay3 <= '0'; elsif clk'event and clk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2; end if; end process; outp <= delay1 and delay2 and (not delay3); end rtl; debounce architecture

Lab Exercise T2 Debounce Simulation using Aldec Active-HDL 4.1