11/11/04 הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות Final Presentation Enhanced Ethernet Card Enhanced Ethernet Card Project num Students: Alex Shpiner Eyal Azran Supervisor: Boaz Mizrahi
Project’s goals: Automatic ping reply Real time Packet analyzer & data collector Real time Network Testing Unit: Predefined transmit rate Accurate measurement of response time Testing parameters are predefined by user
Features of our product: Network tester: MAC/IP addresses of connected cards. Load capacities. Delays measurement Automatic ping replier: Reduce CPU Load
MACMAC CIFCIF TRN RCV ARB FPGA Architecture Shared bus TRP RCP * Configuration units (GNR, MCF) are not shown on this diagram PLXPLX
FPGA Architecture Two modes of working: 1.Tester mode – Sends request packets according to user defined parameters, and collecting data about reply packets. 2.Replier mode – Collect request packets from the net, and automatically replies on them. Due to FPGA size problem, the two modes are two separate projects.
FPGA Architecture T ester mode Echo Request Parameters Echo Request Generator CIFCIF TRNTRN TRP RCP Packet Analyzer Data Collector RCVRCV
Tester mode parameters Inter Packet Gap Total number of test cycles MAC Destination Address IP Destination Addresses Source MAC/IP Addresses
TRP – tester mode DATA FIFO TRANSMITTER EOP FIFO TRN Transmit Parameters Packet Creator Time
RCP – tester mode Data Packet Received FSM AddressType TRP Data Collector CIFCIF Time
FPGA Architecture Replier mode Packet Analyzer CIFCIF RCVRCV RCP TRP TRNTRN Echo Reply Creator
TRP – replier mode DATA FIFO TRANSMITTER EOP FIFO TRN Packet Creator RCP
RCP – replier mode Data Packet Received FSM AddressType TRP Echo received TRP ready
Received packets vs. IPG 1000 Packets were sent with variable IPG
What’s next!?! Add GUI to the driver 1Gbps Ethernet support Optical communication support We advice to modify the following hardware: More memory (SRAM, DRAM) Faster Altera chip to support higher TX/RX rates
Thanks