Conditional Statements  if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression) statements } statements } [ else [ else statements ] statements ] if (total < 60) begin if (total < 60) begin grade = C; grade = C; total_C = total_C + 1; total_C = total_C + 1; end end else if (sum < 75) begin else if (sum < 75) begin grade = B; grade = B; total_B = total_B + 1; total_B = total_B + 1; end end else grade = A; else grade = A;

Conditional Statements  case statement case (case_expression) case (case_expression) case_item_expression {, case_item_expression }: statements case_item_expression {, case_item_expression }: statements …… …… [ default: statements ] [ default: statements ] endcase endcase case (OP_CODE) case (OP_CODE) 2`b10: Z = A + B; 2`b10: Z = A + B; 2`b11: Z = A – B; 2`b11: Z = A – B; 2`b01: Z = A * B; 2`b01: Z = A * B; 2`b00: Z = A / B; 2`b00: Z = A / B; default: Z = 2`bx; default: Z = 2`bx; endcase endcase

Loop Statements  Four loop statements are supported –The for loop –The while loop –The repeat loop –The forever loop  The syntax of loop statements is very similar to that in C language  Most of the loop statements are not synthesizable in current commercial synthesizers

for loop  for (initial condition; terminating condition; increment) begin ….. end  for (i=0;i<32;i=i+1) state[i]=0;  for (i=0;i<32;i=i+2) beginstate[i]=1; state[i+32]=0; state[i+32]=0;end

repeat loop  repeat(constant number)  connot be used to loop on a general logical expression  repeat(128) begin $display( “ count=%d ”,count); count=count+1;end

forever loop  execute forever until the $finish task is encountered.  clock=1 ’ b0; forever #10 clock=~clock;

while loop  while (logical expression) begin ……. ……. end end  while ((i<128) && continue) begin $display( “ count=%d ”, count); i=i+1;end  while ((i<128) && continue) i=i+1;

Example -- ASM designed by HDL This example is referred from “ Digital Design “, M. Morris Mano

Example -- ASM designed by HDL

//RTL description of design example (Fig.8-11) module Example_RTL (S,CLK,Clr,E,F,A); //Specify inputs and outputs //See block diagram Fig input S,CLK,Clr; output E, F; output [4:1] A; //Specify system registers reg [4:1] A; //A register reg E, F; //E and F flip-flops reg [1:0] pstate, nstate; //control register //Encode the states parameter T0 = 2'b00, T1= 2'b01, T2 = 2'b11; //State transition for control logic //See state diagram Fig. 8-11(a) CLK or negedge Clr) if (~Clr) pstate = T0; //Initial state else pstate <= nstate; //Clocked operations (S or A or pstate) case (pstate) T0: if (S) nstate = T1; else nstate = T0; T1: if (A[3] & A[4]) nstate = T2; else nstate = T1; T2: nstate = T0; endcase //Register transfer operations //See list of operation Fig.8-11(b) (posedge CLK) case (pstate) T0: if (S) begin A <= 4'b0000; F <= 1'b0; end T1: begin A <= A + 1'b1; if (A[3]) E <= 1'b1; else E <= 1'b0; end T2: F <= 1'b1; endcase endmodule

Example -- ASM designed by HDL //Test bench for design example module test_design_example; reg S, CLK, Clr; wire [4:1] A; wire [4:1] A; wire E, F; wire E, F; //Instantiate design example Example_RTL dsexp (S,CLK.Clr,E,F,A); initial begin Clr = 0; S = 0; CLK = 0; #5 Clr = 1; S = 1; repeat (32) begin #5 CLK = ~ CLK; end initial $monitor("A = %b E = %b F = %b time = %0d”, A.E.F,$time); endmodule

Simulation results Table 8-2